78Q2132 TDK Corp., 78Q2132 Datasheet - Page 21

• Manufacturer Part Number: 78Q2132
• Description: 1/10base-t Homepna/ethernet Transceiver
• Manufacturer: TDK Corp.

P1R0-14 - PROGRAMMABLE REGISTER MAP, PAGE 1 (continued)
REGISTER
3
4, 5
6, 7
SYMBOL
ISTAT (ISR)
TX_PCOM
RX_PCOM
TYPE
R/W
R/W
R/O
DESCRIPTION
The interrupt status register reports the state of each
interrupt source, regardless of the state of the IMASK
register. The interrupt sources are mapped into this register
in an identical manner as the IMASK register. Furthermore,
any bit may be written and so facilitate software-stimulated
interrupt testing. The appropriate bits in this register must
be cleared for the INTN signal to be cleared.
The 32-bit transmitted data field to be used for out-of-band
communication between PHY management entities. No
protocol for out-of-band management has been defined.
Accessing the low word causes the PHY to send all-0
PCOM’s until the high byte has been accessed. Once
accessed, the next transmitted packet will cause this
register’s contents to be shifted out in the PCOM field of
the transmitted packet. Upon transmission, this register will
read back as all-0’s. A non-null transmitted PCOM will set
the TxPCOM Ready bit in the ISTAT register. An access to
any of the two TxPCOM words will clear the TxPCOM
Ready bit in the ISTAT register.
The 32-bit received data field to be used for out-of-band
communication between PHY management entities. No
protocol for out-of-band management has been defined.
Accessing the low word of the register is sufficient to
ensure that subsequently received packets will not over-
write the register contents. A non-null received PCOM will
set the RxPCOM Valid bit of the ISTAT. Accessing the high
word of the register clears this bit and allows over-writing of
the register by subsequent received packets.
21
HomePNA/Ethernet Transceiver
1/10BASE-TX
78Q2132
Default
0x0000
ALL 0’s
ALL 0’s