CDK2307 Cadeka Microcircuits LLC., CDK2307 Datasheet - Page 10

• Manufacturer Part Number: CDK2307
• Description: Dual, 20/40/65/80msps, 12/13-bit Analog-to-digital Converters
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
©2009 CADEKA Microcircuits LLC
Symbol
Clock Inputs
Timing
Logic Inputs
Logic Outputs
T
T
T
T
ε
T
T
T
V
V
I
I
C
V
V
C
HI
LI
PD
SLP
OVR
AP
RMS
LAT
D
DC
HI
LI
I
HO
LO
L
and resulting switching noise at a minimum.
Parameter
Duty Cycle
Compliance
Input Range
Input Common Mode Voltage
Input Capacitance
Start Up Time Active Mode
Start Up Time Mode
Out Of Range Recovery Time
Aperture Delay
Aperture Jitter
Pipeline Delay
Output Delay (see timing diagram)
Output Delay (see timing diagram)
High Level Input Voltage
Low Level Input Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Max Capacitive Load
Conditions
Differential input swing
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of OVDD
Differential
From Power Down Mode to Active Mode
From Sleep Mode to Active
5pF load on output bits
Relative to CLK_EXT
VOVDD ≥ 3.0V
VOVDD = 1.7V – 3.0V
VOVDD ≥ 3.0V
VOVDD = 1.7V – 3.0V
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VDVDD
Post-driver supply voltage above 2.25V
(1)
0.8
VOVDD-0.1
CMOS, LVDS, LVPECL, Sine Wave
Min
400
1.6
•
0.3
-10
-10
20
VOVDD
3
1
2
0
0
Typ
<0.5
0.8
12
10
2
1
3
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VOVDD -0.3
0.2
Max
900
•
0.8
0.1
80
20
10
10
10
VOVDD
6
5
clk cycles
clk cycles
clk cycles
clk cycles
Units
% high
psrms
mVpp
Vpp
µA
µA
pF
ns
ns
ns
pF
pF
pF
V
V
V
V
V
V
V
10