CDK2308 Cadeka Microcircuits LLC., CDK2308 Datasheet

no-image

CDK2308

Manufacturer Part Number
CDK2308
Description
Dual, 20/40/65/80msps, 10-bit Analog-to-digital Converters
Manufacturer
Cadeka Microcircuits LLC.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CDK2308BILP64
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
CDK2308DILP64
Quantity:
2 000
Company:
Part Number:
CDK2308DILP64
Quantity:
11 630
Data Sheet
CDK2308
Dual, 20/40/65/80MSPS, 10-bit
Analog-to-Digital Converters
Ordering Information
Moisture sensitivity level for all parts is MSL-2A.
©2009 CADEKA Microcircuits LLC
Part Number
CDK2308AILP64
CDK2308BILP64
CDK2308CILP64
CDK2308DILP64
CDK2308AITQ64
CDK2308BITQ64
CDK2308CITQ64
CDK2308DITQ64
F E A T U R E S
n
n
n
n
n
n
n
n
n
n
n
A P P L I C A T I O N S
n
n
n
n
10-bit resolution
20/40/65/80MSPS maximum sampling rate
Ultra-low power dissipation: 24/43/65/78mW
61.6dB SNR at 80MSPS and 8MHz F
Internal reference circuitry
1.8V core supply voltage
1.7V – 3.6V I/O supply voltage
Parallel CMOS output
64-pin QFN package
(TQFP-64 package option also available)
Dual channel
Pin compatible with CDK2307
Medical Imaging
Portable Test Equipment
Digital Oscilloscopes
IF Communication
Speed
20MSPS
40MSPS
65MSPS
80MSPS
20MSPS
40MSPS
65MSPS
80MSPS
IN
Package
QFN-64
QFN-64
QFN-64
QFN-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
Preliminary
General Description
The CDK2308 is a high performance, low power dual Analog-to-Digital Con-
verters (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the com-
plete full scale range.
Several idle modes with fast startup times exist. Each channel can indepen-
dently be powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
Functional Block Diagram
Pb-Free
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
10
10
A m p l i fy t h e H u m a n E x p e r i e n c e
CLK_EXT
Packaging Method
Tray
Tray
Tray
Tray
Tray
Tray
Tray
Tray
www.cadeka.com

Related parts for CDK2308

CDK2308 Summary of contents

Page 1

... The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs. ...

Page 2

... Data Sheet Pin Configuration QFN-64, TQFP- CDK2308 7 QFN-64, TQFP- DVSSCLK 13 14 DVDDCLK CLKP 15 CLKN 16 Pin Assignments Pin No. Pin Name Description 1, 18 Digital and I/O-ring pre driver supply voltage, 1. CM_EXT Common Mode voltage output Analog supply voltage, 1 ...

Page 3

Data Sheet Pin Assignments (Continued) Pin No. Pin Name Description Connect Connect Connect 29 D1_0 Output Data Channel 1 (LSB) 30 D1_1 Output Data Channel 1 31 D1_2 Output Data Channel ...

Page 4

Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper ...

Page 5

Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter DC Accuracy No Missing Codes Offset Error ...

Page 6

... Data Sheet Electrical Characteristics - CDK2308A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SNDR Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...

Page 7

... Data Sheet Electrical Characteristics - CDK2308B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SNDR Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...

Page 8

... Data Sheet Electrical Characteristics - CDK2308C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD=2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SNDR Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...

Page 9

... Data Sheet Electrical Characteristics - CDK2308D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SNDR Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...

Page 10

Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Parameter Clock Inputs ...

Page 11

... Data Sheet CLK_EXT Recommended Usage Analog Input The analog inputs to the CDK2308 is a switched capacitor track-and-hold amplifier optimized for differential opera- tion. Operation at common mode voltages at mid sup- ply is recommended even if performance will be good for the ranges specified. The CM_EXT pin provides a voltage suitable as common mode voltage reference ...

Page 12

... Figure 6. Alternative Input Network Clock Input And Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In the CDK2308 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. ...

Page 13

... The digital outputs can be set in tristate mode by setting the OE_N signal high. ©2009 CADEKA Microcircuits LLC The CDK2308 employs digital offset correction. This means that the output code will be 4096 with the positive and negative inputs shorted together(zero differential). How- ever, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also results in ε ...

Page 14

Data Sheet Table 1: Data Format Description for 2V Differential Input Voltage (IPx - INx) 1.0 V +0.24mV -0.24mV -1.0V Mechanical Dimensions QFN-64 Package aaa Pin 1 ID 0.05 Dia. 1.14 bbb C ...

Page 15

... CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. Inches ...

Related keywords