WM8608 ETC-unknow, WM8608 Datasheet - Page 20

• Manufacturer Part Number: WM8608
• Description: The Wm8608 Comprises A High Performance Multi-channel Pwm Digital Power Amplifier Controller. Simply By Adding Appropriate Power Output Stages A Multi-channel Power Amplifier May Be Built. Six Identical Full Audio Bandwidth Channels, Plus A Reduced B
• Manufacturer: ETC-unknow

WM8608
AUDIO INTERFACE CONTROL
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The register bits controlling audio format, word length and master/slave mode are summarised
below. MS selects audio interface operation in master or slave mode. In Master mode BCLK and
LRCLK are outputs and the frequency of LRCLK is set by the sample rate control bits SR[3:0]. In
Slave mode BCLK and LRCLK are inputs (refer to Table 12 for sample rate control in this case).
Table 11 Audio Data Format Control
Notes:
R2 (02h)
Audio IF
Format
REGISTER
ADDRESS
1.
2.
Right Justified mode does not support 32-bit data.
LRSWAP does not affect the polarity of SUBSWP, the left-right controlling of DINC_LFE is
separate from the other channels.
8
7
6
5
4
3:2
1:0
BIT
BCLKINV
MS
LRSWAP
SUBSWP
LRP
WL[1:0]
FORMAT[1:0]
LABEL
DEFAULT
10
10
0
0
0
0
0
BCLK invert bit (for master and slave
modes)
0 = BCLK not inverted
1 = BCLK inverted
Master / Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Left/Right channel swap
1 = swap left and right data in audio
interface
0 = output left and right data as normal
Front Centre – LFE channel swap
1 = Front Centre right and LFE left
0 = Front Centre left and LFE right
Right, left and I
polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
(as show in e.g. Figure 12)
DSP Mode – A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
Audio Data Format Select
11 = DSP Mode
10 = I
01 = Left justified
00 = Right justified
2
S Format
DESCRIPTION
2
S modes – LRCLK
PP Rev 1.5 March 2004
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