LPC2460 NXP Semiconductors, LPC2460 Datasheet
LPC2460
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LPC2460 Summary of contents
Page 1
... ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO lines. The LPC2460 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts ...
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... Preliminary data sheet 2 C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Medical systems I Protocol converter I Communications 4. Ordering information Table 1. Ordering information Type number Package Name LPC2460FBD208 LQFP208 LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 4.1 Ordering options Table 2. Ordering options Type number Flash (kB) LPC2460FBD208 N LPC2460FET208 N/A ...
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... AD0 A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2460 block diagram LPC2460_2 Preliminary data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64 kB TEST/DEBUG SRAM INTERFACE INTERNAL ARM7TDMI-S ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2460 pinning LQFP208 package Fig 3. LPC2460 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 13 P3[20]/D20/ 14 PWM0[5]/DSR1 LPC2460_2 Preliminary data sheet 1 LPC2460FBD208 52 ball A1 ...
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... PWM0[3]/CTS1 - - TDO 4 P3[12]/D12 V 8 P3[8]/D8 DD(3V3 DD(DCDC)(3V3) SSCORE P2[2]/PWM1[3]/ 16 P1[13]/ENET_RX_DV CTS1/PIPESTAT1 - - TMS 4 P3[3]/D3 P2[3]/PWM1[4]/ 17 P2[6]/PCAP1[0]/ DCD1/PIPESTAT2 RI1/TRACEPKT1 P3[29]/D29/ 4 DBGEN MAT1[0]/PWM1[6] P2[5]/PWM1[6]/ 17 P3[16]/D16/ DTR1/TRACEPKT0 PWM0[1]/TXD1 DD(3V3) DDA P2[7]/RD2/ 17 P4[10]/A10 RTS1/TRACEPKT2 LPC2460 © NXP B.V. 2008. All rights reserved ...
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... MCIPWR/RD1 MCICMD/SCL1 P2[29]/DQMOUT1 4 XTAL2 V 17 P0[22]/RTS1/ SSIO MCIDAT0/TD1 P2[27]/CKEOUT3/ 4 P2[28]/DQMOUT0 MAT3[1]/MOSI0 P1[18]/USB_UP_LED1 DD(3V3) PWM1[1]/CAP1[ DD(DCDC)(3V3) SSIO P4[18]/A18 16 P4[19]/A19 - - P0[28]/SCL0 4 P2[25]/CKEOUT1 P2[19]/CLKOUT1 8 P1[21]/USB_TX_DM1/ PWM1[3]/SSEL0 P2[16]/CAS 12 P2[14]/CS2/ CAP2[0]/SDA1 LPC2460 © NXP B.V. 2008. All rights reserved ...
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... Fast communication chip Pin Symbol P4[4]/A4 16 P4[5]/ P3[26]/D26/ 4 P2[26]/CKEOUT2/ MAT0[1]/PWM1[3] MAT3[0]/MISO0 P0[14]/USB_HSTEN2/ 8 P2[20]/DYCS0 USB_CONNECT2/ SSEL1 P4[2]/A2 12 P1[27]/USB_INT1/ USB_OVRCR1/CAP0[1] P0[10]/TXD2/SDA2/ 16 P2[13]/EINT3/ MAT3[0] MCIDAT3/I2STX_SDA - - P2[18]/CLKOUT0 4 P0[29]/USB_D+1 P1[20]/USB_TX_DP1/ 8 P1[22]/USB_RCV1/ PWM1[2]/SCK0 USB_PWRD1/MAT1[0] P2[21]/DYCS1 12 P2[22]/DYCS2/ CAP3[0]/SCK0 P0[0]/RD1/TXD3/SDA1 16 P4[3]/ LPC2460 © NXP B.V. 2008. All rights reserved ...
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... P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. 2 I/O SCL2 — clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip 2 S-bus specification . 2 S-bus 2 S-bus specification . 2 S-bus specification . ...
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... P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. I/O MCICMD — Command line for SD/MMC interface. 2 I/O SCL1 — clock input/output (this is not an open-drain pin). Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... USB_D+2 — USB port 2 bidirectional D+ line. I/O Port 1: Port bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect block. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip 2 S-bus specification . 2 S-bus 2 S-bus specifi ...
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... P1[12] — General purpose digital input/output pin. I ENET_RXD3 — Ethernet Receive Data (MII interface). I/O MCIDAT3 — Data line 3 for SD/MMC interface. I PCAP0[0] — Capture input for PWM0, channel 0. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... P1[24] — General purpose digital input/output pin. I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver). O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. O PIPESTAT0 — Pipeline Status, bit 0. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip 2 C serial clock (OTG transceiver serial data (OTG transceiver). © NXP B.V. 2008. All rights reserved. ...
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... P2[10] — General purpose digital input/output pin. Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset. I EINT0 — External interrupt 0 input. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... P2[22] — General purpose digital input/output pin. O DYCS2 — SDRAM chip select 2. I CAP3[0] — Capture input for Timer 3, channel 0. I/O SCK0 — Serial clock for SSP0. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip 2 S-bus specification . 2 S-bus 2 S-bus specification . © NXP B.V. 2008. All rights reserved. ...
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... D2 — External memory data line 2. [1] I/O P3[3] — General purpose digital input/output pin. I/O D3 — External memory data line 3. [1] I/O P3[4] — General purpose digital input/output pin. I/O D4 — External memory data line 4. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... P3[18] — General purpose digital input/output pin. I/O D18 — External memory data line 18. O PWM0[3] — Pulse Width Modulator 0, output 3. I CTS1 — Clear to Send input for UART1. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... P3[28] — General purpose digital input/output pin. I/O D28 — External memory data line 28. I CAP1[1] — Capture input for Timer 1, channel 1. O PWM1[5] — Pulse Width Modulator 1, output 5. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... A10 — External memory address line 10. [1] I/O P4[11] — General purpose digital input/output pin. I/O A11 — External memory address line 11. [1] I/O P4[12] — General purpose digital input/output pin. I/O A12 — External memory address line 12. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... P4[26] — General purpose digital input/output pin. O BLS0 — LOW active Byte Lane select signal 0. [1] I/O P4[27] — General purpose digital input/output pin. O BLS1 — LOW active Byte Lane select signal 1. Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2460 being in Reset state. [7] I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... C-bus 400 kHz specification. It requires an external pull-up to provide output 2 C-bus is floating and does not disturb the I Rev. 02 — 1 February 2008 Fast communication chip , but should be isolated to minimize noise and SSCORE but should be isolated to minimize noise and error. LPC2460 DD(3V3 lines. Open-drain © NXP B.V. 2008. All rights reserved ...
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... ARM7TDMI-S processor for little-endian byte order. The LPC2460 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. ...
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... ARM code while retaining most of the ARM’s performance. 7.2 On-chip SRAM The LPC2460 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. ...
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... NXP Semiconductors 3.75 GB Fig 4. LPC2460 memory map 7.4 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... External memory controller The LPC2460 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...
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... Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2460 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...
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... The value of the output register may be read back as well as the current state of the port pins. LPC2460 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...
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... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2460 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB ...
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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2460 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...
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... Compatible with CAN specification 2.0B, ISO 11898-1 . • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. LPC2460_2 Preliminary data sheet Rev. 02 — 1 February 2008 LPC2460 Fast communication chip 2 C interface © NXP B.V. 2008. All rights reserved ...
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... Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.13 10-bit DAC The DAC allows the LPC2460 to generate a variable analog output. The maximum output value of the DAC is V 7.13.1 Features • 10-bit DAC • ...
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... UART3 includes an IrDA mode to support infrared communication. 7.15 SPI serial I/O controller The LPC2460 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...
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... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2460 supports bit rates up to 400 kbit/s (Fast I 7.18.1 Features • standard I • ...
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... Controls include reset, stop and mute options separately for I 7.20 General purpose 32-bit timers/external event counters The LPC2460 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2460. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2460, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2460 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.24.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... Power control The LPC2460 supports a variety of power control features. There are three special modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL ...
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... Each of the peripherals has its own clock divider which provides even better power control. The LPC2460 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the Battery RAM ...
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... System control 7.25.1 Reset Reset has four sources on the LPC2460: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable ...
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... VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if this reset source is enabled in software) to inactivate the LPC2460 when the voltage on the V DD(3V3) at which point the power-on reset circuitry maintains the overall Reset. ...
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... NXP Semiconductors 7.26 Emulation and debugging The LPC2460 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2460 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. ...
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... V DD(3V3) supply voltage is present [2][3] other I/O pins [4] per supply pin [4] per ground pin [5] based on package heat transfer, not device power consumption [6] human body model; all pins Rev. 02 — 1 February 2008 LPC2460 Fast communication chip Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V ...
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... 0 DD(3V3 0 DDA < V < DD(3V3) I Rev. 02 — 1 February 2008 LPC2460 Fast communication chip [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 [2] 2.0 3.3 3.6 2.5 3.3 V DDA - - 100 ...
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... PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz V = 3.3 V; DD(DCDC)(3V3 amb DC-to-DC converter on DC-to-DC converter off OLS DD(3V3 < V < 3 Rev. 02 — 1 February 2008 LPC2460 Fast communication chip [1] Min Typ Max - <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> 150 ...
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... and D . Conditions Rev. 02 — 1 February 2008 Fast communication chip [1] Min Typ 0.2 - 0 [11 1.1 - Min Typ [1][2][ [1][ [1][ [1][ [1][ [ LPC2460 Max Unit - V 2.5 V 2.0 V 0. 44.1 1.9 k Max Unit V V DDA LSB 2 LSB 3 LSB 0 LSB 40 k © NXP B.V. 2008. All rights reserved ...
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... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 5. Figure Figure 5. Rev. 02 — 1 February 2008 Fast communication chip 5. LPC2460 Figure 5. © NXP B.V. 2008. All rights reserved ...
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... LSB (ideal (LSB ) IA ideal ). D ). Rev. 02 — 1 February 2008 Fast communication chip (1) 1018 1019 1020 1021 1022 1023 V V DDA SSA 1 LSB = 1024 LPC2460 offset gain error error 1024 002aac046 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors AD0[y] Fig 6. Suggested ADC interface - LPC2460 AD0[y] pin LPC2460_2 Preliminary data sheet LPC2XXX 20 k SAMPLE SSIO, SSCORE Rev. 02 — 1 February 2008 LPC2460 Fast communication chip R vsi AD0[y] V EXT 002aad586 © NXP B.V. 2008. All rights reserved ...
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... DD(3V3) Conditions see Figure 8 see Figure must reject as EOP; see Figure 8 must accept as EOP; see Figure 8 Rev. 02 — 1 February 2008 LPC2460 Fast communication chip Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175 2 ...
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... Preliminary data sheet over specified ranges. DD(3V3) Conditions Min cy(clk) T cy(clk 0 amb measured in SPI Master mode; see Figure 9 Rev. 02 — 1 February 2008 LPC2460 Fast communication chip [1] [2] Typ Max Unit - 24 MHz - 1000 ...
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... SE0/EOP skew PERIOD FDEOP t su(SPI_MISO) Rev. 02 — 1 February 2008 Fast communication chip t CHCX t CLCH T cy(clk) 002aaa907 extended source EOP width: t receiver EOP width: t sampling edges 002aad326 LPC2460 FEOPT , t EOPR1 EOPR2 002aab561 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC24XX Fig 10. LPC2460 USB interface on a self-powered device LPC24XX Fig 11. LPC2460 USB interface on a bus-powered device LPC2460_2 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D V V SSIO, ...
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... RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D 1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D 2 USB_UP_LED2 Fig 12. LPC2460 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2460_2 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...
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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 13. LPC2460 USB OTG port configuration: VP_VM mode LPC2460_2 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D 1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D 2 V BUS Fig 14. LPC2460 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2460_2 Preliminary data sheet FLAGA ENA OUTA 5 V LM3526-L ...
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... USB_D+2 USB_D 2 USB_UP_LED2 Fig 15. LPC2460 USB OTG port configuration: USB port 1 host, USB port 2 host 11.2 Suggested boot memory interface solutions ‘a_m’ and ‘a_b’ in the following figures refer to the highest order address line of the memory chip and the highest order microcontroller’s address line used respectively. ...
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... NXP Semiconductors Fig 17. Booting from a single 16-bit memory chip LPC2460_2 Preliminary data sheet CS1 16-bit BLS[1] MEMORY LB BLS[0] IO[15:0] D[15:0] A[a_m:0] A[a_b:1] 002aad323 Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... JEDEC JEITA MS-026 Rev. 02 — 1 February 2008 Fast communication chip detail 0.75 1.43 1 0.12 0.08 0.08 0.45 1.08 EUROPEAN PROJECTION LPC2460 SOT459 1. 1.08 0 ISSUE DATE 00-02-06 03-02-20 © NXP B.V. 2008. All rights reserved ...
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... 15.1 15.1 0.8 12.8 12.8 0.15 14.9 14.9 REFERENCES JEDEC JEITA - - - Rev. 02 — 1 February 2008 Fast communication chip detail 0.08 0.12 0.1 EUROPEAN PROJECTION LPC2460 SOT950 ISSUE DATE 06-06-01 06-06-14 © NXP B.V. 2008. All rights reserved ...
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... Reduced Media Independent Interface Secure Digital/MultiMediaCard Single Ended Zero Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Preliminary data sheet - description”: pin RSTOUT changed from 1 3.3 V “Features”: ’Controller supports’ changed from ’2 kbit, 4 kbit, and 8 kbit’ to Preliminary data sheet - Rev. 02 — 1 February 2008 LPC2460 Fast communication chip Supersedes LPC2460_1 - © NXP B.V. 2008. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. SoftConnect — trademark of NXP B.V. GoodLink — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 1 February 2008 LPC2460 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Application information . . . . . . . . . . . . . . . . . 56 11.1 Suggested USB interface solutions . . . . . . . . 56 11.2 Suggested boot memory interface solutions . 60 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 62 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 64 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 65 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 66 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 66 Rev. 02 — 1 February 2008 LPC2460 Fast communication chip continued >> © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2460 All rights reserved. Date of release: 1 February 2008 Document identifier: LPC2460_2 ...