MPC8321E Freescale Semiconductor, Inc, MPC8321E Datasheet

MPC8321E

Manufacturer Part Number

MPC8321E

Description

Mpc8321e Powerquicc Ii Pro Processor

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MPC8321E.pdf (80 pages)

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Freescale Semiconductor

Advance Information

MPC8323E

PowerQUICC™ II Pro Integrated

Communications Processor

Family Hardware Specifications

This document provides an overview of the MPC8323E

PowerQUICC™ II Pro processor features. The MPC8323E

is a cost-effective, highly integrated communications

processor that addresses the requirements of several

networking applications, including ADSL SOHO and

residential gateways, modem/routers, industrial control, and

test and measurement applications. The MPC8323E extends

current PowerQUICC™ offerings, adding higher CPU

performance, additional functionality, and faster interfaces,

while addressing the requirements related to time-to-market,

price, power consumption, and board real estate. This

document describes the MPC8323E, and unless otherwise

noted, the information also applies to the MPC8323,

MPC8321E, and MPC8321.

To locate published errata or updates for this document, refer

to the MPC8323E product summary page on our website

listed on the back cover of this document or, contact your

local Freescale sales office.

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

11. I

12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

19. HDLC, BISYNC, Transparent, and Synchronous

20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . .47

22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

24. System Design Information . . . . . . . . . . . . . . . . . . . .74

25. Document Revision History . . . . . . . . . . . . . . . . . . . .77

26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .78

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .6

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .10

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .12

6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . .13

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

8. Ethernet and MII Management . . . . . . . . . . . . . . . . . .18

9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Document Number: MPC8323EEC

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Contents

Rev. 1, 06/2007

Related parts for MPC8321E

MPC8321E Summary of contents

Page 1

... This document describes the MPC8323E, and unless otherwise noted, the information also applies to the MPC8323, MPC8321E, and MPC8321. To locate published errata or updates for this document, refer to the MPC8323E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office ...

Page 2

... MPC8323E. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A block diagram of the MPC8323E is shown in ...

Page 3

Additionally, the QUICC Engine block can also support a UTOPIA level 2 capable of supporting 31 multi-PHY (MPC8323E- and MPC8323-specific). The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing ...

Page 4

... Mbps Ethernet/IEEE 802.3® standard — IP support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing — ATM protocol through UTOPIA interface (note that the MPC8321 and MPC8321E do not support the UTOPIA interface) — HDLC /transparent up to 70-Mbps full-duplex — ...

Page 5

Security Engine The security engine is optimized to handle all the algorithms associated with IPSec, IEEE 802.11i® standard, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units ...

Page 6

Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8323E. The MPC8323E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are ...

Page 7

Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8323E. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating ...

Page 8

Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8323E for the 3.3-V signals, respectively. Overvoltage Waveform Undervoltage Waveform Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling 2.1.3 Output Driver ...

Page 9

Input Capacitance Specification Table 4 describes the input capacitance for the CLKIN pin in the MPC8323E. Parameter/Condition Input capacitance for all pins except CLKIN Input capacitance for CLKIN Note: 1. The external clock generator should be able to drive ...

Page 10

Power Characteristics 3 Power Characteristics The estimated typical power dissipation for this family of MPC8323E devices is shown in CSB QUICC Engine Frequency (MHz) Frequency (MHz) 133 200 133 200 Notes: 1. The values do not include I/O supply power ...

Page 11

estimated to consume 0.05 W (under normal operating DD conditions and ambient temperature). 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8323E. 4.1 DC Electrical Characteristics ...

Page 12

RESET Initialization 5 RESET Initialization This section describes the AC electrical specifications for the reset initialization timing requirements of the MPC8323E. Table 9 provides the reset initialization AC timing specifications for the reset component(s). Table 9. RESET Initialization Timing Specifications ...

Page 13

Reset Signals DC Electrical Characteristics Table 11 provides the DC electrical characteristics for the MPC8323E reset signals mentioned in Table 11. Reset Signals DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage ...

Page 14

DDR1 and DDR2 SDRAM Table 13 provides the DDR2 capacitance when Dn_GV Table 13. DDR2 SDRAM Capacitance for Dn Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note This parameter is sampled (peak-to-peak) ...

Page 15

DDR1 and DDR2 SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR1 and DDR2 SDRAM interface. 6.2.1 DDR1 and DDR2 SDRAM Input AC Timing Specifications Table 16 provides the input AC timing specifications for ...

Page 16

DDR1 and DDR2 SDRAM Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with Dn_GV Parameter ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS output setup with ...

Page 17

Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t MDQS MDQS Figure 6 shows the DDR1 and DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 t DDKHMP MDQS[n] MDQ[x] Figure 6. ...

Page 18

DUART 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8323E. 7.1 DUART DC Electrical Characteristics Table 20 provides the DC electrical characteristics for the DUART interface of the MPC8323E. Table 20. ...

Page 19

The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 DC Electrical Characteristics All MII and RMII drivers and receivers ...

Page 20

Ethernet and MII Management Table 23. MII Transmit AC Timing Specifications (continued) At recommended operating conditions with OV Parameter/Condition TX_CLK data clock fall V (max Note: 1. The symbols used for timing specifications follow the pattern of ...

Page 21

Table 24. MII Receive AC Timing Specifications (continued) At recommended operating conditions with OV Parameter/Condition RX_CLK clock fall time V (max Note: 1. The symbols used for timing specifications follow the pattern of t inputs and t ...

Page 22

Ethernet and MII Management 8.2.2.1 RMII Transmit AC Timing Specifications Table 23 provides the RMII transmit AC timing specifications. Table 25. RMII Transmit AC Timing Specifications At recommended operating conditions with OV Parameter/Condition REF_CLK clock REF_CLK duty cycle REF_CLK to ...

Page 23

Table 26. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with OV Parameter/Condition REF_CLK clock fall time V (max Note: 1. The symbols used for timing specifications follow the pattern of t inputs and t ...

Page 24

Ethernet and MII Management 8.3.1 MII Management DC Electrical Characteristics MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 27. MII Management DC ...

Page 25

Figure 13 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 13. MII Management Interface Timing Diagram 9 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the ...

Page 26

Local Bus Table 30. Local Bus General Timing Parameters (continued) Parameter LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid Local bus clock ...

Page 27

Figure 15 through Figure 17 show the local bus signals. LCLK[n] Input Signals: LAD[0:15] Input Signal: LGTA Output Signals: LBCTL/LBCKE/LOE Output Signals: LAD[0:15] LALE Figure 15. Local Bus Signals, Nonspecial Signals Only LCLK T1 T3 GPCM Mode Output Signals: LCS[0:3]/LWE ...

Page 28

JTAG LCLK GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 17. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV JTAG This section describes ...

Page 29

Table 31. JTAG Interface DC Electrical Characteristics (continued) Characteristic Input low voltage Input current 10.2 JTAG AC Electrical Characteristics This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8323E. Table 32 provides the ...

Page 30

JTAG Table 32. JTAG AC Timing Specifications (Independent of CLKIN) At recommended operating conditions (see Parameter JTAG external clock to output high impedance: Boundary-scan data Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of ...

Page 31

Figure 21 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs Figure 22 provides the test access port timing diagram. JTAG External Clock TDI, TMS t JTKLOX ...

Page 32

This section describes the DC and AC electrical characteristics for the Electrical Characteristics Table 33 provides the DC electrical characteristics for the I At recommended operating conditions ...

Page 33

Table 34. I All values refer to V (min) and V (max) levels (see IH IL Parameter Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free ...

Page 34

PCI 12 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8323E. 12.1 PCI DC Electrical Characteristics Table 35 provides the DC electrical characteristics for the PCI interface of the MPC8323E. Table 35. ...

Page 35

Table 37 shows the PCI AC timing specifications at 33 MHz. Table 37. PCI AC Timing Specifications at 33 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedence Input setup to clock Input hold ...

Page 36

Timers Figure 27 shows the PCI output AC timing conditions. CLK Output Delay High-Impedance Output Figure 27. PCI Output AC Timing Measurement Condition 13 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8323E. ...

Page 37

Figure 28 provides the AC test load for the timers. Output 14 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8323E. 14.1 GPIO DC Electrical Characteristics Table 11 provides the DC electrical characteristics ...

Page 38

IPIC Figure 29 provides the AC test load for the GPIO. Output 15 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8323E. 15.1 IPIC DC Electrical Characteristics Table 42 provides the ...

Page 39

SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8323E. 16.1 SPI DC Electrical Characteristics Table 44 provides the DC electrical characteristics for the MPC8323E SPI. Characteristic Output high voltage Output low voltage ...

Page 40

TDM/SI Figure 31 and Figure 32 represent the AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 31 shows the SPI timing in ...

Page 41

Table 46. TDM/SI DC Electrical Characteristics (continued) Characteristic Input low voltage Input current 17.2 TDM/SI AC Timing Specifications Table 47 provides the TDM/SI input and output AC timing specifications. Table 47. TDM/SI AC Timing Specifications Characteristic TDM/SI outputs—External clock delay ...

Page 42

... UTOPIA 18 UTOPIA This section describes the UTOPIA DC and AC electrical specifications of the MPC8323E. The MPC8321E and MPC8321 do not support UTOPIA. 18.1 UTOPIA DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the MPC8323E UTOPIA. Table 48. UTOPIA DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...

Page 43

Figure 35 provides the AC test load for the UTOPIA. Output Figure 36 and Figure 37 represent the AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is ...

Page 44

HDLC, BISYNC, Transparent, and Synchronous UART 19.1 HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Table 50 provides the DC electrical characteristics for the MPC8323E HDLC, BISYNC, transparent, and synchronous UART protocols. Table 50. HDLC, BISYNC, Transparent, and Synchronous ...

Page 45

Table 52. Synchronous UART AC Timing Specifications Characteristic Outputs—Internal clock delay Outputs—External clock delay Outputs—Internal clock high impedance Outputs—External clock high impedance Inputs—Internal clock input setup time Inputs—External clock input setup time Inputs—Internal clock input hold time Inputs—External clock input ...

Page 46

USB Figure 40 shows the timing with internal clock. Serial CLK (Output) Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable. Figure 40. AC Timing (Internal Clock) Diagram 20 USB This section provides the AC ...

Page 47

Table 54. USB General Timing Parameters (continued) Parameter Skew among RXP, RXN, and RXD Notes: 1. The symbols used for timing specifications follow the pattern of t and t (first two letters of functional block)(state)(signal) USB receive signals skew (RS) ...

Page 48

Package and Pin Listings Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns ...

Page 49

Pinout Listings Table 55 shows the pin list of the MPC8323E. Signal MEMC_MDQ0 MEMC_MDQ1 MEMC_MDQ2 MEMC_MDQ3 MEMC_MDQ4 MEMC_MDQ5 MEMC_MDQ6 MEMC_MDQ7 MEMC_MDQ8 MEMC_MDQ9 MEMC_MDQ10 MEMC_MDQ11 MEMC_MDQ12 MEMC_MDQ13 MEMC_MDQ14 MEMC_MDQ15 MEMC_MDQ16 MEMC_MDQ17 MEMC_MDQ18 MEMC_MDQ19 MEMC_MDQ20 MEMC_MDQ21 MEMC_MDQ22 MEMC_MDQ23 MEMC_MDQ24 MEMC_MDQ25 MEMC_MDQ26 ...

Page 50

Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal MEMC_MDQ29 MEMC_MDQ30 MEMC_MDQ31 MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDQS0 MEMC_MDQS1 MEMC_MDQS2 MEMC_MDQS3 MEMC_MBA0 MEMC_MBA1 MEMC_MBA2 MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 ...

Page 51

Table 55. MPC8323E PBGA Pinout Listing (continued) Signal MEMC_MCKE MEMC_MCK MEMC_MCK MEMC_MODT RST_LAD0/LAD0 RST_LAD1/LAD1 RST_LAD2/LAD2 RST_LAD3/LAD3 RST_LAD4/LAD4 RST_LAD5/LAD5 RST_LAD6/LAD6 RST_LAD7/LAD7 RST_LAD8/LAD8 RST_LAD9/LAD9 RST_LAD10/LAD10 RST_LAD11/LAD11 RST_LAD12/LAD12 RST_LAD13/LAD13 RST_LAD14/LAD14 RST_LAD15/LAD15 RST_LA16/LA16 RST_LA17/LA17 RST_LA18/LA18 RST_LA19/LA19 RST_LA20/LA20 RST_LA21/LA21 RST_LA22/LA22 RST_LA23/LA23 RST_LA24/LA24 RST_LA25/LA25 RST_LCS0/LCS0 MPC8323E ...

Page 52

Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal RST_LCS1/LCS1 RST_LCS2/LCS2 RST_LCS3/LCS3 RST_LWE0/LWE0 RST_LWE1/LWE1 RST_LBCTL/LBCTL RST_LALE/RST_LALE/M1LALE/M2LALE CFG_RESET_SOURCE[0]/LSDA10/LGPL0 CFG_RESET_SOURCE[1]/LSDWE/LGPL1 RST_LOE/LSDRAS/LGPL2/LOE CFG_RESET_SOURCE[2]/LSDCAS/LGPL3 LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 PD_XLB_CLOCK_OUT/LCLK0/ PD_MG2XLB_ENC_CLOCK/CORE_CLK_OUT PD_XLB2MG_DDR_CLOCK/LCLK1/ PD_MG2XLB_ENC_SYNC UART_SOUT1/MSRCID0 (DDR ID)/LSRCID0 UART_SIN1/MSRCID1 (DDR ID)/LSRCID1 UART_CTS1/MSRCID2 (DDR ID)/LSRCID2 UART_RTS1/MSRCID3 (DDR ...

Page 53

Table 55. MPC8323E PBGA Pinout Listing (continued) Signal IRQ2 IRQ3 IRQ4 IRQ5 IRQ6/CKSTOP_OUT IRQ7/CKSTOP_IN CFG_CLKIN_DIV CFG_LBIU_MUX_EN TCK TDI TDO TMS TRST TEST_MODE QUIESCE HRESET PORESET SRESET CLKIN CLKIN PCI_SYNC_OUT RTC_PIT_CLOCK PCI_SYNC_IN/PCI_CLK PCI_CLK0/clkpd_cerisc1_ipg_clkout/DPTC_OSC PCI_CLK1/clkpd_half_cemb4ucc1_ipg_clkout/ CLOCK_XLB_CLOCK_OUT PCI_CLK2/clkpd_third_cesog_ipg_clkout/ cecl_ipg_ce_clock MPC8323E PowerQUICC™ II Pro ...

Page 54

Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal MVREF1 MVREF2 PCI_INTA /IRQ_OUT PCI_RESET_OUT PCI_AD0/MSRCID0 (DDR ID) PCI_AD1/MSRCID1 (DDR ID) PCI_AD2/MSRCID2 (DDR ID) PCI_AD3/MSRCID3 (DDR ...

Page 55

Table 55. MPC8323E PBGA Pinout Listing (continued) Signal PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C_BE0 PCI_C_BE1 PCI_C_BE2 PCI_C_BE3 PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM M66EN ...

Page 56

Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PA0/SER1_TXD[0]/TDMA_TXD[0]/USBTXN GPIO_PA1/SER1_TXD[1]/TDMA_TXD[1]/USBTXP GPIO_PA2/SER1_TXD[2]/TDMA_TXD[2] GPIO_PA3/SER1_TXD[3]/TDMA_TXD[3] GPIO_PA4/SER1_RXD[0]/TDMA_RXD[0]/USBRXP GPIO_PA5/SER1_RXD[1]/TDMA_RXD[1]/USBRXN GPIO_PA6/SER1_RXD[2]/TDMA_RXD[2]/USBRXD GPIO_PA7/SER1_RXD[3]/TDMA_RXD[3] GPIO_PA8/SER1_CD/TDMA_REQ/USBOE GPIO_PA9 TDMA_CLKO GPIO_PA10/SER1_CTS/TDMA_RSYNC GPIO_PA11/CE_TRB_PIN2/TDMA_STROBE GPIO_PA12/SER1_RTS/TDMA_TSYNC/CE_PIO0 GPIO_PA13/CLK9/BRGO9/CE_PIO1 GPIO_PA14/CLK11/BRGO10/CE_PIO2 GPIO_PA15/CE_TRB_PIN3/BRGO7/CE_PIO3 GPIO_PA16/CE_TRB_PIN4/ LA0 (LBIU) GPIO_PA17/CE_TRB_PIN1/ LA1 (LBIU) GPIO_PA18/Enet2_TXD[0]/SER2_TXD[0]/ TDMB_TXD[0]/LA2 (LBIU) GPIO_PA19/Enet2_TXD[1]/SER2_TXD[1]/ TDMB_TXD[1]/LA3 ...

Page 57

Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PA26/Enet2_RX_ER/SER2_CD/TDMB_REQ/ LA10 (LBIU) GPIO_PA27/Enet2_TX_ER/TDMB_CLKO/LA11 (LBIU) GPIO_PA28/Enet2_RX_DV/SER2_CTS/ TDMB_RSYNC/LA12 (LBIU) GPIO_PA29/Enet2_COL/RXD[4]/SER2_RXD[4]/ TDMB_STROBE/LA13 (LBIU) GPIO_PA30/Enet2_TX_EN/SER2_RTS/ TDMB_TSYNC/LA14 (LBIU) GPIO_PA31/Enet2_CRS/SDET LA15 (LBIU) GPIO_PB0/Enet3_TXD[0]/SER3_TXD[0]/ TDMC_TXD[0]/CE_PIO4 GPIO_PB1/Enet3_TXD[1]/SER3_TXD[1]/ TDMC_TXD[1]/CE_PIO5 GPIO_PB2/Enet3_TXD[2]/SER3_TXD[2]/ TDMC_TXD[2]/CE_PIO6 GPIO_PB3/Enet3_TXD[3]/SER3_TXD[3]/ TDMC_TXD[3]/CE_PIO7 GPIO_PB4/Enet3_RXD[0]/SER3_RXD[0]/ TDMC_RXD[0]/CE_PIO8 GPIO_PB5/Enet3_RXD[1]/SER3_RXD[1]/ TDMC_RXD[1]/CE_PIO9 GPIO_PB6/Enet3_RXD[2]/SER3_RXD[2]/ TDMC_RXD[2]/CE_PIO10 GPIO_PB7/Enet3_RXD[3]/SER3_RXD[3]/ ...

Page 58

Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PB17/BRGO1/CE_EXT_REQ1 GPIO_PB18/Enet4_TXD[0]/SER4_TXD[0]/ TDMD_TXD[0]/CE_PIO11 GPIO_PB19/Enet4_TXD[1]/SER4_TXD[1]/ TDMD_TXD[1]/CE_PIO12 GPIO_PB20/Enet4_TXD[2]/SER4_TXD[2]/ TDMD_TXD[2]/CE_PIO13 GPIO_PB21/Enet4_TXD[3]/SER4_TXD[3]/ TDMD_TXD[3]/CE_PIO14 GPIO_PB22/Enet4_RXD[0]/SER4_RXD[0]/ TDMD_RXD[0]/CE_PIO15 GPIO_PB23/Enet4_RXD[1]/SER4_RXD[1]/ TDMD_RXD[1]/CE_PIO16 GPIO_PB24/Enet4_RXD[2]/SER4_RXD[2]/ TDMD_RXD[2]/CE_PIO17 GPIO_PB25/Enet4_RXD[3]/SER4_RXD[3]/ TDMD_RXD[3] GPIO_PB26/Enet4_RX_ER/SER4_CD/TDMD_REQ GPIO_PB27/Enet4_TX_ER/TDMD_CLKO GPIO_PB28/Enet4_RX_DV/SER4_CTS/ TDMD_RSYNC GPIO_PB29/Enet4_COL/RXD[4]/SER4_RXD[4]/ TDMD_STROBE GPIO_PB30/Enet4_TX_EN/SER4_RTS/ TDMD_TSYNC GPIO_PB31/Enet4_CRS/SDET GPIO_PC0/UPC1_TxDATA[0]/SER5_TXD[0] GPIO_PC1/UPC1_TxDATA[1]/SER5_TXD[1] ...

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Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PC10/UPC1_RxDATA[2]/SER5_RXD[2] GPIO_PC11/UPC1_RxDATA[3]/SER5_RXD[3] GPIO_PC12/UPC1_RxDATA[4] GPIO_PC13/UPC1_RxDATA[5]/LSRCID0/CE_PIO18 GPIO_PC14/UPC1_RxDATA[6]/LSRCID1/CE_PIO19 GPIO_PC15/UPC1_RxDATA[7]/LSRCID2/CE_PIO20 GPIO_PC16/UPC1_TxADDR[0] GPIO_PC17/UPC1_TxADDR[1]/LSRCID3/CE_PIO21 GPIO_PC18/UPC1_TxADDR[2]/LSRCID4/CE_PIO22 GPIO_PC19/UPC1_TxADDR[3]/LDVAL/CE_PIO23 GPIO_PC20/UPC1_RxADDR[0] GPIO_PC21/UPC1_RxADDR[1] GPIO_PC22/UPC1_RxADDR[2] GPIO_PC23/UPC1_RxADDR[3] GPIO_PC24/UPC1_RxSOC/SER5_CD GPIO_PC25/UPC1_RxCLAV GPIO_PC26/UPC1_RxPRTY/CE_EXT_REQ2 GPIO_PC27/UPC1_RxEN GPIO_PC28/UPC1_TxSOC GPIO_PC29/UPC1_TxCLAV/SER5_CTS GPIO_PC30/UPC1_TxPRTY GPIO_PC31/UPC1_TxEN/SER5_RTS GPIO_PD0/SPIMOSI/CE_TRB_PIN5 GPIO_PD1/SPIMISO/CE_TRB_PIN6 GPIO_PD2/SPICLK/CE_TRB_PIN7 GPIO_PD3/SPISEL/CE_TRB_PIN8 GPIO_PD4/SPI_MDIO/CE_MUX_MDIO GPIO_PD5/SPI_MDC/CE_MUX_MDC GPIO_PD6/CLK8/BRGO16/CE_EXT_REQ3 GPIO_PD7/GTM1_TIN1/GTM2_TIN2/CLK5 GPIO_PD8/GTM1_TGATE1/GTM2_TGATE2/CLK6 GPIO_PD9/GTM1_TOUT1/CE_PIO25 ...

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Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PD10/GTM1_TIN2/GTM2_TIN1/CLK17 GPIO_PD11/GTM1_TGATE2/GTM2_TGATE1 GPIO_PD12/GTM1_TOUT2/GTM2_TOUT1/ CE_PIO28 GPIO_PD13/GTM1_TIN3/GTM2_TIN4/BRGO8 GPIO_PD14/GTM1_TGATE3/GTM2_TGATE4/ CE_PIO30 GPIO_PD15/GTM1_TOUT3/CE_PIO31 GPIO_PD16/GTM1_TIN4/GTM2_TIN3/CE_PIO29 GPIO_PD17/GTM1_TGATE4/GTM2_TGATE3/ CE_PIO27 GPIO_PD18/GTM1_TOUT4/GTM2_TOUT3/ CE_PIO24 GPIO_PD19/CE_RISC1_INT/CE_EXT_REQ4/ CE_PIO26 GPIO_PD20/CLK18/BRGO6 GPIO_PD21/CLK16/BRGO5/UPC1_CLKO GPIO_PD22/CLK4/BRGO9/UCC2_CLKO GPIO_PD23/CLK3/BRGO10/UCC3_CLKO GPIO_PD24/CLK10/BRGO2/UCC4_CLKO GPIO_PD25/CLK13/BRGO16/UCC5_CLKO GPIO_PD26/CLK2/BRGO4/UCC1_CLKO GPIO_PD27/CLK1/BRGO3 GPIO_PD28/CLK19/BRGO11 GPIO_PD29/CLK15/BRGO8 GPIO_PD30/CLK14 GPIO_PD31/CLK7/BRGO15 GV ...

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Table 55. MPC8323E PBGA Pinout Listing (continued) Signal Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin This ...

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Clocking 22 Clocking Figure 43 shows the internal distribution of clocks within the MPC8323E. MPC8323E ce_clk to QUICC Engine Block QUICC Engine PLL CFG_CLKIN_DIV CLKIN The primary clock source for the MPC8323E can be one of two inputs, CLKIN or ...

Page 63

The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected ...

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Clocking See the “QUICC Engine PLL Multiplication Factor” section and the “QUICC Engine PLL Division Factor” section in the MPC8323E PowerQUICC™ II Pro Communications Processor Reference Manual for more information. The DDR SDRAM memory controller will operate with a frequency ...

Page 65

System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. encodings for the system PLL. As described in Section 22, “Clocking,” configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock ...

Page 66

Clocking CFG_CLKIN_DIV_B 1 at Reset High High High High High High High High High High High High High High High Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low 1 CFG_CLKIN_DIV_B is only used ...

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Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 60 in Table 60 should be considered reserved. RCWL[COREPLL] 0-1 2-5 nn 0000 00 0001 01 0001 ...

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Clocking 22.6 QUICC Engine PLL Configuration The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. shows the multiplication factor encodings for the QUICC Engine PLL. Table 61. QUICC Engine PLL Multiplication Factors RCWL[CEPMF] 00000–00001 00010 00011 00100 ...

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Suggested PLL Configurations To simplify the PLL configurations, the MPC8323E might be separated into two clock domains. The first domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and ...

Page 70

Thermal Table 64. Package Thermal Characteristics for PBGA (continued) Characteristic Junction-to-package top Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other ...

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Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the ...

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Thermal where junction-to-ambient thermal resistance (°C/W) θ junction-to-case thermal resistance (°C/W) θ case-to-ambient thermal resistance (°C/W) θ device related and cannot be influenced by the user. The user controls ...

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Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Interface material vendors include the following: Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu ...

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System Design Information interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. × θ where case temperature of the package (° ...

Page 75

Each circuit should be placed as close as possible to the specific AV noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of package, without ...

Page 76

System Design Information output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and R OV /2. R then becomes the resistance of ...

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... I C pins, Ethernet Management MDIO pin, and IPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, see AN3361, MPC8321E/MPC8323E PowerQUICC™ Design Checklist, Rev Document Revision History Table 66 provides a revision history for this hardware specification. ...

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Ordering Information 26 Ordering Information This section presents ordering information for the devices discussed in this document, and it shows an example of how the parts are marked. Ordering information for the devices fully covered by this document is provided ...

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Part Marking Parts are marked as in the example shown in Figure 46. Freescale Part Marking for PBGA Devices MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor Figure 46. MPCnnnnetppaaar core/platform MHZ ATWLYYWW ...

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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power ...

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