MT8HTF12864AY-1GA Micron Semiconductor Products, MT8HTF12864AY-1GA Datasheet - Page 12

• Manufacturer Part Number: MT8HTF12864AY-1GA
• Description: 256mb, 512mb, 1gb X64, Sr 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 13:
PDF: 09005aef80e2ff8d/Source: 09005aef80e2ff59
HTF8C32_64_128x64A.fm - Rev. F 10/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
between valid commands; Address bus inputs are switching; Data
pattern is same as I
Precharge power-down current: All device banks idle;
t
stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
t
inputs are stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are
switching; Data bus inputs are switching
Active power-down current: All device banks
open;
t
address bus inputs are stable; Data bus inputs are
floating
Active standby current: All device banks open;
t
between valid commands; Other control and address bus inputs are
switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
t
between valid commands; Address bus inputs are switching; Data bus
inputs are switching
Operating burst read current: All device banks open; Continuous
burst reads; I
t
between valid commands; Address bus inputs are switching; Data bus
inputs are switching
Burst refresh current:
t
Other control and address bus inputs are switching; Data bus inputs
are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control
and address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks
interleaving reads; I
AL =
t
valid commands; Address bus inputs are stable during deselects; Data
bus inputs are switching
RC =
RAS =
CK =
CK =
CK =
RAS =
RAS =
RAS =
RFC (I
RRD =
t
t
RCD (I
t
t
t
DD
RC (I
CK (I
CK (I
CK (I
t
t
t
t
t
RAS MIN (I
RAS MAX (I
RAS MAX (I
RAS MAX (I
RRD (I
) interval; CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
DD
DD
OUT
),
DDR2 I
Values are shown for the MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus inputs are
); CKE is HIGH, S# is HIGH; Other control and address bus
); CKE is LOW; Other control and
DD
) - 1 ×
t
RAS =
DD
),
= 0mA; BL = 4, CL = CL (I
DD
t
), AL = 0;
DD
DD
DD
DD
RCD =
OUT
t
),
CK (I
4W
),
),
),
DD
t
RAS MIN (I
t
RCD =
t
t
t
= 0mA; BL = 4, CL = CL (I
RP =
RP =
RP =
t
CK =
Specifications and Conditions (Die Revision E) – 1GB
t
DD
RCD (I
t
);
CK =
t
t
t
DD
RP (I
RP (I
RP (I
t
t
t
RCD (I
CK (I
CK =
), AL = 0;
DD
DD
t
DD
DD
DD
CK (I
); CKE is HIGH, S# is HIGH between
DD
); CKE is HIGH, S# is HIGH between
t
DD
); CKE is HIGH, S# is HIGH
); CKE is HIGH, S# is HIGH
); CKE is HIGH, S# is HIGH
CK (I
); REFRESH command at every
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
); CKE is HIGH, S# is HIGH
DD
DD
t
DD
),
CK =
), AL = 0;
t
),
RC =
t
RC =
t
CK (I
DD
t
t
RC (I
CK =
),
t
t
CK =
t
RC (I
DD
CK =
t
CK =
DD
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
CK (I
DD
t
),
OUT
CK (I
t
CK (I
t
),
CK (I
12
DD
= 0mA;
DD
),
DD
DD
),
);
),
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol -1GA
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
4R
2P
3P
0
1
5
6
7
1,040
1,520 1,280 1,080 1,000
1,520 1,280 1,080 1,000
2,120 1,880 1,720 1,680 1,640
3,400 2,680 2,240 2,160 2,080
920
480
480
400
560
56
80
56
-80E/
-800
Electrical Specifications
720
880
400
400
320
480
56
80
56
©2003 Micron Technology, Inc. All rights reserved.
-667
680
800
320
320
240
440
56
80
56
-53E
560
760
320
320
240
360
56
80
56
-40E Units
560
720
280
280
240
320
840
840
56
80
56
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA