MT8HTF12864AY-1GA Micron Semiconductor Products, MT8HTF12864AY-1GA Datasheet - Page 7

• Manufacturer Part Number: MT8HTF12864AY-1GA
• Description: 256mb, 512mb, 1gb X64, Sr 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

General Description
Serial Presence-Detect Operation
PDF: 09005aef80e2ff8d/Source: 09005aef80e2ff59
HTF8C32_64_128x64A.fm - Rev. F 10/07 EN
The MT8HTF3264A, MT8HTF6464A, and MT8HTF12864A DDR2 SDRAM modules are
high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules
organized in a x64 configuration. These DDR2 SDRAM modules use internally config-
ured, 4-bank (256Mb, 512Mb) or 8-bank (1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS. Output data is referenced to both edges of DQS as well as to both edges of
CK.
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
module, permanently disabling hardware write protect.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2003 Micron Technology, Inc. All rights reserved.
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