MT8VDDT12832UY-6 Micron Semiconductor Products, MT8VDDT12832UY-6 Datasheet - Page 12

• Manufacturer Part Number: MT8VDDT12832UY-6
• Description: 128mb, 256mb, 512mb X32, Dr 100-pin Ddr Udimm
• Manufacturer: Micron Semiconductor Products

Figure 4:
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
Mode Register Definition Diagram
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. The CAS Latency Table
indicates the operating frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
* M14 and M13 (BA1 and BA0)
* M13 and M12 (BA1and BA0)
128MB Module Address Bus
256MB, 512MB Module Address Bus
must be “0, 0” to select the
must be “0, 0” to select the
base mode register (vs. the
base mode register (vs. the
extended mode register).
extended mode register).
0*
14
BA1
0*
0*
13
13
BA0
BA1
0*
12
12
A12 A11
BA0
Operating Mode
11
11
A11
Operating Mode
10
10
A10
A10
M12 M11
0
0
-
9
9
A9
A9
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
0
0
-
8
8
A8
A8
M10
0
0
-
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
M6
0
0
CAS Latency BT
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
4
12
M6-M0
M3
0
1
Valid
Valid
3
3
-
Burst Length
Burst Length
M2
2
0
0
0
0
1
1
1
1
2
A2 A1 A0
CAS Latency
A2 A1 A0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
1
2.5
2
M0
0
1
0
1
0
1
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
0
Burst Length
Interleaved
Burst Type
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
2
4
8
Mode Register Definition
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