SMM150 SUMMIT Microelectronics, Inc:, SMM150 Datasheet
SMM150
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SMM150 Summary of contents
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... Interface Figure 1 – Applications using the SMM150 Controller to control the Voltage Margining of a DC/DC Converter. Note: This is an applications example only. Some components and values are not shown. © SUMMIT Microelectronics, Inc. 2006 • INTRODUCTION The SMM150 is a highly accurate power supply voltage supervisor and environmental monitor with provisions for voltage margining of the monitored supply ...
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... MUP/MDN pin will return the TRIM output pin to a high impedance state thus allowing the converter to return to its nominal operating voltage. The SMM150 has two additional input pins and one additional output pin. The input pins, COMP1 and COMP2, are high impedance inputs, each connected to a comparator and compared against the internal reference (VREF, 0 ...
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... INTERNAL BLOCK DIAGRAM VDD VDD_CAP GND 50kΩ MUP MDN 50kΩ Interface SCL SDA WP Figure 2 – SMM150 Controller Internal Block Diagram. PACKAGE AND PIN CONFIGURATION 28 Pad QFN Top View Pin SCL GND NC 3 SMM150 A1 or ...
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... Power supply of the part. VDD External capacitor input used to filter the internal VDD supply rail. Ground of the part. The SMM150 ground pin should be connected to the ground of the device under control star point ground. PCB GND layout should take into consideration ground drops. ...
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... TL See Pin Descriptions while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual )(Base Hysteresis). For example REF 2075 3.0 01/27/07 SMM150 ° +85 ° (Commercial).............. + ………..………….…….…TBD Min ...
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... MARGIN Summit Microelectronics, Inc Notes VREF=1.25V VREF=0.5V Notes Update period for ADC conversion and DAC update T = (X)(1.8ms) where: MARG_UPDATE X=step number of possible 256 and 1 step=5mV Note 1 – See Figure 4 2075 3.0 01/27/07 SMM150 Min. Typ. Max Unit 1.24 1.25 1.26 V 0.495 0.500 0.505 ± -1.0 +1.0 % 0.75 Min. ...
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... SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Note 1/ Note 1/ Noise suppression t t HIGH t LOW HD:DAT SU:DAT HD:SDA Figure 3. Basic I C Serial Interface Timing 2075 3.0 01/27/07 SMM150 Min Typ Max 0 100 4.7 4.0 - 4.7 Note 1/ 4.7 4.0 4.7 0.2 3.5 0.2 1000 300 250 0 100 (For W rite O peration Only) ...
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... For DC/DC SMM150 receives an I MUP/MDN pin is de-asserted. When not margining, the TRIM pin on the SMM150 high impedance state. The voltage on the TRIM pin is buffered and applied to the ADC at the beginning of a margin cycle to ensure the converter is margined from its nominal setpoint. converter’ ...
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... MARGINING OPERATION POWER OK? YES INPUT VTRIM TO ADC DUMP ADC INTO DAC DAC DRIVES BRICK (TRIM OUTPUT LO-Z) INPUT VOUT TO ADC ADC EQUAL TARGET? NO YES 1. HOLD DAC 2. CLEAR STATUS REGISTER 3. WAIT FOR NEXT COMMAND Figure 5 - SMM150 Margin Flow Chart 2075 3.0 01/27/07 SMM150 INCREMENT/ DECREMENT DAC 9 ...
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... The part can be programmed to trigger the FAULT# pin when either COMPx comparator has exceeded the range. The READY and FAULT# outputs of the SMM150 are active as long as the triggering limit remains in a fault condition. programmable active high/low open drain output indicates that its’ set point. ...
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... Figure 6 – Typical applications schematic which shows the SMM150 controlling a 3.3V in/1.5V out DC/DC converter. Care should be taken to filter DC/DC converter noise from the SMM150 VDD supply pin. This is accomplished with optional components R3, C1, C2, C3 and C10. This example, using a 1.25V VREF, also shows the COMP1/2 pins monitoring the DC/DC converter VOUT set 1.7V on COMP1 and ...
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... VNom 0.3 = TRIM output saturation voltage Vnom = Nominal (non-trimmed output voltage) Figure 8 - Simplified TRIM circuit of a non-isolated DC-DC converter connects to SMM150 TRIM output Summit Microelectronics, Inc Figure 7 below displays the internal trimming circuit for a typical isolated DC-DC converter. In this example, the converter uses positive trimming, i.e., an increase in voltage at the TRIM pin causes an increase in output voltage ...
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... SDA 2 1 SCL 2 C serial bus connections to program the SMM150. The SMM150 has a 2075 3.0 01/27/07 SMM150 2 C serial bus format so that it can be directly An example of the connection This will ensure proper device Pin 10, Reserved Pin 9, 5V Pin 8, Reserved Pin 7, 10V ...
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... The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMM150. Refer to Table 2 for an example of the unique address handling of the SMM150. The device type identifier for the memory array, the configuration registers and the command and status registers are accessible with the same slave address ...
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... Table 2 – Example device addresses allowed by the SMM150. Summit Microelectronics, Inc COMMAND AND STATUS REGISTERS Writes and reads of the command and status registers are shown in Figures 17 and 18. GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMM150 graphical user interface (GUI) is highly recommended ...
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... Data ( Data (16 SMM150 ...
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... Data ( Data (16 SMM150 ...
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... Bus Address Data ( SMM150 ...
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... Max converter Settling Time is 2.5ms, Margin I pins disabled active low. VREF set to 1.25V RC1 The default device ordering number is SMM150NC-356, is programmed as described above and tested over the commercial temperature range. See Application Note 46 for a complete description of the Configuration Register settings and corresponding Windows GUI control ...
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... PACKAGE OUTLINES Summit Microelectronics, Inc 28 Pad QFN 2075 3.0 01/27/07 SMM150 20 ...
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... PACKAGE OUTLINES (CONTINUED) Summit Microelectronics, Inc TM 20 Ball Ultra CSP 2075 3.0 01/27/07 SMM150 21 ...
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... FlipChip International, LLC. 2075 3.0 01/27/ Ball Ultra CSP Ball A1 Identifier Summit Part Number 100% Sn, RoHS compliant Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) Date Code Y = Single digit year (4=2004, 5=2005, etc) to scale L is for the QFN (N package) for data sheet updates. SMM150 22 ...