SMM764 SUMMIT Microelectronics, Inc:, SMM764 Datasheet
SMM764
Related parts for SMM764
SMM764 Summary of contents
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... Internal REFERENCE Figure 1 – Applications schematic using the SMM764 controller to actively control the output levels DC/DC converters while also providing power-on/off, cascade sequencing and output margining. Note: This is an applications example only. Some pins, components and values are not shown. ...
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... Ordering Information…..……………………….… ……30 Terminology And Definitions……………………… …..31 Legal Notice………………………………………… …..32 2098 1.1 6/29/2005 SMM764 Preliminary Information 2 ...
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... Figure 2 – Example power supply sequencing and system start-up initialization using the SMM764. Cascade sequencing ensures that all supplies in the previous sequence position are valid before the next channel is released. Using the SMM764 any order of supply sequencing can be applied. GENERAL DESCRIPTION The SMM764 is a highly integrated and accurate power supply controller, monitor, and sequencer ...
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... D CAP D TRIM A TRIM_CAP A Active DC Output Control TM (ADOC ) TRIM D TRIM_CAP D VREF FILT_CAP Figure 3 – SMM764 Internal Functional Block Diagram. Summit Microelectronics, Inc VDD_CAP 3.6V or Power 5.5V Supply Regulator Arbitrator UVLO Control Temperature Sensor Memory, Limit and Status Registers 2098 1.1 6/29/2005 SMM764 Preliminary Information PWR_ON ...
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... PWR_ON the part will sequence the supplies on, during the falling edge the part will sequence the supplies off. This pin must be tied high through an external pull-up resistor. Note: The SMM764 does not monitor for faults during power-on/off sequencing. FS# (Force Shutdown open drain active low bi-directional pin. FS# is used to immediately turn off all converter enable signals (PUP outputs) when a fault is detected ...
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... SEQ_LINK (Sequence-Link™ open drain bi-directional pin. This pin should be attached to other Sequence-Link devices, during linked operation. SEQ_LINK must be pulled high through an external pull-up resistor when multiple Sequence-Link devices are used. When the SMM764 is not used with another Sequence-Link device, SEQ_LINK should be tied directly to ground. ...
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... PACKAGE AND PIN CONFIGURATION SDA SCL A2 MR# PWR_ON FS# FAULT# HEALTHY RST# AIN1 AIN2 GND Summit Microelectronics, Inc 48 LEAD TQFP TOP VIEW 2098 1.1 6/29/2005 SMM764 Preliminary Information 36 VMB 35 TRIM_CAPC 34 TRIMC 33 PUPC 32 CAPC 31 VMC 30 TRIM_CAPD 29 TRIMD 28 PUPD 27 CAPD 26 VMD ...
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... VDD floating TRIM sourcing maximum current TRIM sinking maximum current Depends on TRIM range of DC-DC converter Max acceptable board and cap leakage VDD = 2.7V VDD = 5.0V VDD = 2.7V VDD = 5.0V 2098 1.1 6/29/2005 SMM764 Preliminary Information ° +85 ° (Commercial) .............. +70 1 ............................ 6.0V to 14. Min Typ Max 2 ...
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... V 3.5V SENSE Internal VREF=1.25V, total PUPx I < 3ma SINK VDD_CAP voltage at which the PUP, RST#, HEALTHY and FAULT#, FS#, PWR_ON SEQ_LINK, outputs are valid VDD_CAP rising VDD_CAP falling 2098 1.1 6/29/2005 SMM764 Preliminary Information Min Typ Max Unit 0 VDD_CAP 0 VDD_CAP 0 VDD_CAP 0 ...
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... Note 1 - The formula for the total ADC inaccuracy is: [((ADC read voltage) +/- INL)*(range of gain error)]+range of offset error Summit Microelectronics, Inc Notes Minimum resolution for which no missing codes are guaranteed Conversion rate = 500Hz Note 1 Note 1 Note 1 2098 1.1 6/29/2005 SMM764 Preliminary Information Min Typ Max Unit 10 Bits 10 Bits ...
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... Time for ADC conversion of all 9 channels Update period for ADOC of channels A – D Slow Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1µF Fast Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1µF 2098 1.1 6/29/2005 SMM764 Preliminary Information Min Typ Max -25 t +25 DPON -25 t +25 DPOFF ...
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... Note 1/ 250 0 Noise suppression Configuration registers Memory array HIGH LOW HD:DAT SU:DAT HD:SDA Figure 4 - Basic I C Serial Interface Timing 2098 1.1 6/29/2005 SMM764 Preliminary Information 100kHz 400kHz Typ Max Min Typ Max 100 0 400 1.3 0.6 1.3 0.6 0.6 0.6 3.5 0.2 0.9 0.2 1000 1000 300 300 ...
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... TIMING DIAGRAMS (CONTINUED) Sequence Position PUP t A DPONA VM A PUP PUP PUP Figure 5 - The SMM764 cascade sequencing the supplies on and then monitoring for fault conditions. Sequence Position PUP PUP PUP t C DPOFFC VM C PUP t D DPOFFD ...
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... APPLICATIONS INFORMATION DEVICE OPERATION POWER SUPPLY The SMM764 can be powered by either a 12V input through the 12VIN pin 3.3V or 5.0V input through the VDD pin. The 12VIN pin feeds an internal programmable regulator that internally generates either 5.5V or 3.6V. A voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the VDD input ...
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... This ensures that the converters have reached their full supply voltage before they are enabled. Summit Microelectronics, Inc On the rising edge of the PWR_ON pin the SMM764 will wait a power-on delay time (t X pins. channels in the first sequence position (position 1) and ...
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... Fault-Triggered conditions, those caused by UV/OV violations or a sequence termination timer expiration. The mode in which either a forced-shutdown or a power-off occurs effects how or whether the SMM764 will restart, and the number of allowable retries permitted. TEMPERATURE SENSOR ACCURACY The internal temperature sensor accuracy is ±5 -40 to +85 of the SMM764 die and the ambient temperature ...
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... X position are below the programmed OFF thresholds. At this point, the SMM764 will move to the next sequence position and begin to timeout the power-off delay times for the associated channels. This process continues until all of the channels in the sequence have turned off and are below their OFF thresholds ...
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... SMM764 has entered monitoring mode power-off sequence. This condition will continue until an I PROGRAMMABLE RETRIES In the event of a persistent system fault, the SMM764 a force-shutdown may be programmed to limit the number of Fault- Triggered restarts it will allow. This programmable setting ensures that the SMM764 will not enter a hiccup-mode susceptibility to transient fault conditions ...
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... Figure 10 - Timing Sequence recovering from a VDD_CAP Power ‘Brown-Out’ Summit Microelectronics, Inc 2.5V (Figure 10), an internal undervoltage lockout (UVLO) circuit will reset all internal logic. Once power has recovered above 2.6V the SMM764 will restart Command-Triggered power-off had been issued. 2.6V 2098 1.1 6/29/2005 ...
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... Gnd 2 Gnd Figure 11 – SMM764 Distributed power applications schematic. The accuracy of the external reference (U10) sets the accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2% Summit Microelectronics, Inc U2 15 FILT_CAP VDD_CAP 14 VREF 12VIN VDD ...
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... MR SDA 2 1 SCL 2 C serial bus connections to program the SMM764. Note that the MR# 2098 1.1 6/29/2005 Preliminary Information 2 C serial bus format so that it can be directly An example of the connection This will ensure proper device Pin 10, Reserved Pin 9, 5V Pin 8, Reserved Pin 7, 10V ...
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... The address pointer for the configuration registers, memory, command and status registers and ADC allowing used registers must be set before data can be read from the SMM764. This is accomplished by a issuing a dummy write command, which is simply a write command that or 1011 as BIN BIN is not followed by a Stop condition ...
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... Command and Status Registers, BA2 BA1 BA0 One Configuration Registers, ADC Conversion Readout BA2 BA1 0 2-k Bits of General-Purpose Memory BA2 BA1 1 Configuration Registers Table 1 - Address bytes used by the SMM764. 2098 1.1 6/29/2005 SMM764 Preliminary Information Memory writes and . Writes and reads of the BIN ...
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... Data Data (16 SMM764 ...
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... Write BIN Bus Address Data ( Read BIN SMM764 ...
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... Bus Address Data ( SMM764 ...
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... Bus Address 10-Bit ADC Data SMM764 ...
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... RC1 The default device ordering number is SMM764FC-285 programmed with the register contents as shown above and tested over the commercial temperature range with a VREF setting of 1.25V. Other standard external VREF voltage settings that can be specified and tested are values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300. ...
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... Summit Microelectronics, Inc 48 PIN TQFP PACKAGE (A) BSC (B) (B) (A) Ref Jedec M S-026 0.037 - 0.041 0.95 - 1.05 0.047 (1.2) B 2098 1.1 6/29/2005 Preliminary Information Inches (Millim eters) 0.02 (0.5) 0.007 - 0.011 (0.17 - 0.27) DETAIL "A" MAX. 0.002 - 0.006 (0.05-0.15) DETAIL "B" SMM764 BSC 0.039 Ref (1.00 Min Max 0.018 - 0.030 (0.45 - 0.75) 29 ...
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... Part Number Suffix (see page 28) Specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. The calibrated VREF voltage Temp Range settings are standard values of: 1.024, 1.225, 1.250, 2.048, C=Commercial 2.500, 3.000 or 3.300 Blank=Industrial 2098 1.1 6/29/2005 SMM764 Preliminary Information 30 ...
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... ADC Analog to Digital Converter. Converts analog voltage to digital voltage. SMM764 represents all measured voltages by 10-bit digital reading. Retries The number of times the SMM764 will restart after a Fault-Triggered power-off or force- shutdown. Restart When the SMM764 begins power on sequencing, includes initial power-on sequence. ...
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... Copyright 2005 SUMMIT MICROELECTRONICS, Inc. are registered trademarks of Summit Microelectronics Inc trademark of Philips Corporation ADOC and Sequence-Link Summit Microelectronics, Inc NOTICE http://www.summitmicro.com/errata/SMM764 PROGRAMMABLE ANALOG FOR A DIGITAL WORLD™ 2098 1.1 6/29/2005 SMM764 Preliminary Information 32 ...
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... Document Rev. Description 1.0 Preliminary datasheet 1.1 VIH & VIL modified for 0.8 VIH and 0.2 VIL logic levels. TRIM CAP description changed to be left floating when unused. Summit Microelectronics, Inc Date 6/29/2005 2098 1.1 6/29/2005 SMM764 Preliminary Information Owner ...