HM-65162 Intersil Corporation, HM-65162 Datasheet
HM-65162
Related parts for HM-65162
HM-65162 Summary of contents
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... Copyright © Intersil Americas Inc. 2002. All Rights Reserved HM-65162/883 Description The HM-65162/883 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the ...
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... Functional Diagram ROW A4 ADDRESS A5 BUFFER HM-65162/883 128 X 128 ROW MEMORY ARRAY DECODER 128 128 COLUMN DECODER AND DATA INPUT / OUTPUT (X8 COLUMN ADDRESS BUFFER A10 189 DQ0 THRU 8 DQ7 ...
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... ICCEN VCC = 5.5V 0mA, Current E = 0.8V Data Retention ICCDR HM-65162B/883 0mA, Supply Current VCC = 2.0V VCC - 0.3V HM-65162/883 0mA, VCC = 2.0V VCC - 0.3V HM-65162C/883 0mA, VCC = 2.0V VCC - 0.3V Functional Test FT VCC = 4.5V (Note 3) NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent 50pF (min) - for CL greater than 50pF, access time by 0 ...
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... TABLE 2. HM-65162/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested. (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS Read/Write/ (1) TAVAX VCC = 4.5V Cycle Time and 5.5V Address (2) TAVQV VCC = 4.5V Access Time and 5.5V Chip Enable (3) TELQV VCC = 4.5V Access Time and 5.5V Output Enable (5) TGLQV VCC = 4.5V Access Time and 5.5V ...
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... TABLE 3. HM-65162/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC PARAMETER SYMBOL CONDITIONS Input CIN VCC = Open, Capacitance F = 1MHz, All Measurements Referenced To Device Ground I/O CI/O VCC = Open, Capacitance F = 1MHz, All Measurements Referenced To Device Ground Chip Enable to (4) TELQX VCC = 4.5V and Output ON 5.5V Output Enable (6) TGLQX VCC = 4.5V and to Output ON 5 ...
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... To write, addresses must be stable, E low and W falling low for a period no shorter than TWLWH. Data in is referenced with the rising edge of W, (TDVWH and TWHDX). While addresses are changing, W must be high. When W falls low, the I/O pins are still in the output state for a period of TWLQZ HM-65162/883 (1) TAVAX (2) TAVQV (5) TGLQV (3) TELQV ...
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... The following rules ensure data retention: 1. Chip Enable (E) must be held high during data retention; within VCC -0.3V to VCC +0.3V RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected V CC 4.5V E HM-65162/883 (10) TAVAX (22) TAVWH (14) (11) TELWH TWHAX (12) TAVWL (13) TWLWH TGHQZ (15) ...
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... F2 F2 DQ4 F2 DQ3 F2 NOTES: All resistors 47kW ±5 100kHz ±10 ÷ ÷ ÷ F13 = F12 ÷ 2. VCC = 5.5V ±0.5V. VIH = 4.5V ±10%. VIL = -0.2V to +0.4V 0.01µF Min. 195 IOL HM-65162/883 CLCC TOP VIEW ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com HM-65162/883 GLASSIVATION: Type: SiO Thickness: 8k WORST CASE CURRENT DENSITY HM-65162/883 VCC A8 196 2 ±1k Å ...