HM-65162 Intersil Corporation, HM-65162 Datasheet - Page 6

• Manufacturer Part Number: HM-65162
• Description: 2kx8 Asynchronous Cmos Static Ram
• Manufacturer: Intersil Corporation

Timing Waveforms
NOTE:
Addresses must remain stable for the duration of the read
cycle. To read, G and E must be ≤ VIL and W ≥ VIH. The
output buffers can be controlled independently by G while E
is low. To execute consecutive read cycles, E may be tied
NOTE:
To write, addresses must be stable, E low and W falling low
for a period no shorter than TWLWH. Data in is referenced
with the rising edge of W, (TDVWH and TWHDX). While
addresses are changing, W must be high. When W falls low,
the I/O pins are still in the output state for a period of TWLQZ
1. W is High for a Read Cycle.
1. G is Low throughout Write Cycle.
ADDRESS
W
Q
E
D
ADDRESS
G
Q
E
(12) TAVWL
(6) TGLQX
(16) TWLQZ
(4) TELQX
(2) TAVQV
(3) TELQV
FIGURE 2. WRITE CYCLE I
(17) TDVWH
FIGURE 1. READ CYCLE
HM-65162/883
(22) TAVWH
(5) TGLQV
(1) TAVAX
(10) TAVAX
(20) TWLEH
193
(13) TWLWH
(11) TELWH
low continuously until all desired locations are accessed.
When E is low, addresses must be driven by stable logic
levels and must not be in the high impedance state.
and input data of the opposite phase to the outputs must not
be
simultaneously with the W line transitioning low or after the
W transition, the output will remain in a high impedance
state. G is held continuously low.
(9) TAVQX
applied,
TDVEH
(21)
(Bus
(8) TGHQZ
(19) TWHQX
(7) TEHQZ
contention).
(18) TWHDX
If
E
(14) TWHAX
transitions
low