HM-65642F Intersil Corporation, HM-65642F Datasheet - Page 6
HM-65642F
Manufacturer Part Number
HM-65642F
Description
8kx8 Asynchronous Cmos Static Ram
Manufacturer
Intersil Corporation
Datasheet
1.HM-65642F.pdf
(11 pages)
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data Retention voltage and supply current are guaran-
teed over the operating temperature range. The following
rules ensure data retention:
Read Cycles
VCCOR
GND
VCC
4.5V
Q
A
VIH
E2
TAVQV
ADDRESS 1
TAVAX
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
FIGURE 1. DATA RETENTION
HM-65642/883
DATA 1
DATA RETENTION MODE
TAXQX
225
1. The RAM must be kept disabled during data retention. This is ac-
2. During power-up and power-down transitions, E2 must be held
3. The RAM can begin operating one TAVAX after VCC reaches the
ADDRESS 2
complished by holding the E2 pin between -0.3V and GND.
between -0.3V and 10% of VCC.
minimum operating voltage of 4.5V.
DATA 2
TAVAX