FIN1049 Fairchild Semiconductor, FIN1049 Datasheet
FIN1049
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FIN1049 Summary of contents
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... LVDS inputs and translates them to LVTTL outputs. The LVDS levels have a typical differential output swing of 350mV which provide for low EMI at ultra low power dissi- pation even at high frequencies. The FIN1049 can accept LVPECL inputs for translating from LVPECL to LVDS. The En and Enb inputs are ANDed together to enable/disable the outputs ...
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Function Table Inputs Outputs (LVTTL ENb OUT1 HIGH Logic Level L LOW Logic Level or OPEN X Don’t Care Z High Impedance Note 1: Any unused ...
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Absolute Maximum Ratings Supply Voltage ( LVDS DC Input Voltage ( LVDS DC Output Voltage (V ) OUT Driver Short Circuit Current (I ) Continuous 10mA OSD Storage Temperature Range (T ) STG Max Junction Temperature ...
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AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter t Differential Propagation Delay LOW-to-HIGH PLHD t Differential Propagation Delay HIGH-to-LOW PHLD t Differential Output Rise Time (20% to 80%) TLHD t Differential Output Fall ...
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Required Specifications 1. Human Body Model ESD and Machine Model ESD should be measured using MIL-STD-883C method 3015.7 standard. Note: C 15pF, includes all probe and jig capacitances L FIGURE 1. Differential Receiver Voltage Definitions Test Circuit TABLE 1. Receiver ...
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Required Specifications (Continued) Note A: R 100 L Note and Distributed O T FIGURE 3. LVDS Output Propagation Delay and Transition Time Test Circuit FIGURE 4. LVTTL Input to LVDS Output AC Waveform www.fairchildsemi.com ...
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Required Specifications (Continued) Note A: R 100 L Note and Distributed O T Note: R1 1000 , R 950 S Note: V 2.4V TST FIGURE 5. LVDS Output Enable / Disable Delay Test Circuit ...
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Required Specifications (Continued) Note and Distributed O T Note: R 100 and R 950 L S FIGURE 7. LVTTL Output Propagation Delay and Transition Time Test Circuit FIGURE 8. LVDS Input to LVTTL Output ...
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Required Specifications (Continued) Note and Distributed O T Note: R 100 , R1 1000 , and R 950 L S FIGURE 9. LVTTL Output Enable / Disable Test Circuit FIGURE 10. LVTTL Output Enable ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...