NCP5222 ON Semiconductor, NCP5222 Datasheet - Page 14

• Manufacturer Part Number: NCP5222
• Description: High Performance Dual-channel / Two-phase Synchronous Buck Controller For Notebook Power System
• Manufacturer: ON Semiconductor

I
Equations 5, 6, 7, 8, 15, and 16 gives:
I
where
certain regulation window in case of any fault or non−ideal
conditions, such as the sharing switch is broken or has too
high on resistance, the injection current I
limits as $9 mA. As a result, V
range as
resistance and the two phases matches perfectly, the
current−sense input voltages in the two phases are equal, that
is
Using of Equations 15, 16, and 21 gives
PWM Operation
forced PWM mode and power−saving skip mode, selected
by two different voltage levels at EN pin for each channel,
respectively. The operation modes can be external preset or
on−line programmed.
share one input power rail. The both channels / phases
operate at a fixed 300 kHz normal switching frequency in
FB2
O2
k
k
I
v 1 )
Share
Where I
IL1_IFB2
IL2_IFB2
To maintain the output voltage V
In an Ideal case that the sharing switch has very small on
There are two available operation modes, which are
The two channels / phases controlled by the NCP5222
1 )
is the loading current in the power rail V
+ k
+
R
R
@
I
I
I
L1
L1
L2
IL2_IFB2
21
24
DCR
+ G
+ G
+ 1x10
+ 1x10
O1
R
R
1 )
@ DCR
+
+
21
24
@ 0.8 * 8 @ 10
is the loading current in the power rail V
DCR
DCR
IFB2
IFB2
1
R
R
DCR
DCR
DCR
@ 0.8 ) 9 @ 10
@ I
21
24
@ k
1
−3
−3
O2
1
1
@ G
@ G
@ k
CS1
@ V
2
@ k
1
@ k
1
@
@
* k
@ k
@ k
@ k
CS1
R
R
ICS1
ICS2
CS1
CS1
@ I
ref2
CS21
CS11
CS2
CS1
CS1
IL1_IFB2
O1
+ I
R
* 1 )
@ R
R
@ R
) DCR
) DCR
−6
CS22
@ I
@ I
* DCR
) DCR
CS12
) R
) R
L2
@ R
R
−6
ICS1
ICS2
ON_S
O1
O1
O2
@ DCR
@ R
@ I
CS22
21
CS12
) I
) I
@ k
@ k
2
2
has a limited adjustable
R
R
O1
v V
21
@ k
@ k
2
2
11
14
) R
O2
CS1
CS2
@ k
@ k
@ DCR
@ DCR
O2
O2
) k
2
CS2
CS2
O2
@ k
@ V
FB2
of the phase 2 in
CS2
CS2
21
@ DCR
@ DCR
CS2
IL1_IFB2
ref1
@ k
has magnitude
2
@ I
1
O2
) R
O2
IL1_IFB2
1
2
. Using of
) k
(eq. 18)
(eq. 19)
(eq. 20)
(eq. 21)
(eq. 22)
(eq. 23)
(eq. 24)
O1
21
http://onsemi.com
, and
@ k
IL2_IFB2
) k
IL1_IFB2
IL2_IFB2
14
continuous−conduction mode (CCM). To reduce the
common input ripple and capacitors, the two channels /
phases operate 180° interleaved in CCM. To speed up
transient response and increase system sampling rate, an
internal 1.2 MHz high−frequency oscillator is employed. A
digital circuitry divides down the high−frequency clock
CLK_H and generates two interleaved 300 kHz clocks
(CLK1 and CLK2), which are delivered to the two PWM
control blocks as normal operation clocks.
Forced−PWM Operation (FPWM Mode)
1.95 V, the corresponding channel of the NCP5222 works
under forced−PWM mode with fixed 300 kHz switching
frequency. In this mode, the low−side gate−drive signal is
forced to be the complement of the high−side gate−drive
signal and thus the converter always operates in CCM. This
mode allows reverse inductor current, in such a way that it
provides more accurate voltage regulation and fast transient
response. During soft−start operation, the NCP5222
automatically runs in FPWM mode regardless of the EN
pin’s setting to guarantee smooth powering up.
Pulse−Skipping Operation (Skip Mode)
2.65 V, and then the corresponding channel works in
pulse−skipping enabled operation. In medium and high load
range, the converter still runs in CCM, and the switching
frequency is fixed to 300 kHz. If the both channels run in
CCM, they operate interleaved. In light load range, the
converter automatically enters diode emulation and skip
mode to maintain high efficiency. The PWM on−time in
discontinuous−conduction mode (DCM) is adaptively
controlled to be similar to the PWM on−time in CCM.
Transient Response Enhancement (TRE)
CCM, the minimum response delay time is one switching
period in the worst case. To further improve transient
response, a transient response enhancement circuitry is
introduced to the NCP5222. The controller continuously
monitors the COMP signal, which is the output voltage of
the error amplifier, to detect load transient events. A desired
stable close−loop system with the NCP5222 has a ripple
voltage in the COMP signal, which peak−to−peak value is
normally in a range from 200 mV to 500 mV. There is a
threshold voltage in each channel made in a way that a
filtered COMP signal pluses an offset voltage. Once a large
@ I
If the voltage level at the EN pin is a medium level around
Skip mode is enabled by pulling EN pin higher than
For a conventional trailing−edge PWM controller in
O1
* k
IL2_IFB2
@ I
O2
(eq. 17)