NCP5222 ON Semiconductor, NCP5222 Datasheet - Page 15

• Manufacturer Part Number: NCP5222
• Description: High Performance Dual-channel / Two-phase Synchronous Buck Controller For Notebook Power System
• Manufacturer: ON Semiconductor

load transient occurs, the COMP signal is possible to exceed
the threshold and then TRE is tripped in a short period,
which is typically around one normal switching cycle. In this
short period, the controller runs at higher frequency and
therefore has faster response. After that the controller comes
back to normal operation.
Protection Funtions
functions for the power system, which include input power
supply undervoltage lock out, output overcurrent protection,
output overvoltage protection, output undervoltage
protection, and thermal shutdown protection. The priority of
the protections from high to low as: 1. Thermal protection
and input power supply undervoltage lockout; 2. Output
overvoltage protection; 3. Output overcurrent protection
and output undervoltage protection.
Input Power Supply Undervoltage Lock Out (UVLO)
power supplies (V
controller itself. The two UVLO functions make it possible
to have flexible power sequence between V
the power systems. The start threshold of V
the starting threshold of V
Output Overcurrent Protection (OCP)
The current through each channel is continuously monitored
with differential current sense. If inductor current exceeds
the current threshold, the high−side gate drive will be turned
off cycle−by−cycle. In the meanwhile, an internal OC fault
timer will be triggered. If the fault still exists after about
53 ms, the corresponding channel latches off, both the
high−side MOSFET and the low−side MOSFET are turned
off. The fault remains set until the system has shutdown and
re−applied V
states.
internally fixed to 30 mV. The current limit can be
programmed by the inductor’s DCR and the current−sense
resistor divider with R
current limit is
The DC current limit is
where V
f
current is equal to output loading current I
SW
The NCP5222 provides comprehensive protection
The NCP5222 provides UVLO functions for both input
The NCP5222 protects converter if overcurrent occurs.
Current limit threshold V
In the dual−channel mode, the steady−state inductor DC
is 300 kHz normal switching frequency.
IN
is input supply voltage of the power stage, and
I
OC
CC
+ I
and/or the enable signal EN has toggled
I
OC(Peak)
OC(Peak)
IN
and V
CS1
CC
+
TH_OC
*
and R
CC
is 4.25 V.
k
V
2 @ V
CS
V
) of the power stage and
O
TH_OC
@ V
@ DCR
between CS+ and CS−is
CS2
IN
@ f
. The inductor peak
IN
* V
SW
Omax
IN
IN
@ L
O
and V
is 3.6 V, and
per channel,
(eq. 25)
(eq. 26)
http://onsemi.com
CC
for
15
so that the overcurrent threshold I
loading current I
triggered in the normal operation, the worst case need to be
considered, in which the maximum load step in one power
rail comes just after the two phases are sharing the maximum
load from the other power rail. In this case, the two
overcurrent thresholds need to be set as
and
current−sense threshold V
Use of Equations 29, 30, and 31 leads to:
Output Overvoltage Protection (OVP)
loads from over voltage. OVP limit is typically 115% of the
nominal output voltage level, and the hysteresis of the OV
detection comparator is 5% of the nominal output voltage.
If the OV event lasts less than 1.5 ms, the controller remains
normal operation when the output of the OV comparator is
released, otherwise an OV fault is latched after 1.5 ms. After
the fault is latched, the high−side MOSFET is latched off and
the low−side MOSFET will be on and off responding to the
output of the OV detection comparator. The fault remains set
until the system has shutdown and re−applied V
the enable signal EN has toggled states.
Output Undervoltage Protection (UVP)
undervoltage. UVP limit is typically 80% of the nominal
output voltage level. If the output voltage is below this
threshold, a UV fault is set. If an OV protection is set before,
the UV fault will be masked. If no OV protection set, an
internal fault timer will be triggered. If the fault still exists
after about 27 ms, the corresponding channel is latches off,
both the high−side MOSFET and the low−side MOSFET are
I
In two−phase operation mode, to make sure the OCP is not
I
I
The both phases also has the same internal overcurrent
I
I
An OVP circuit monitors the feedback voltages to prevent
A UVP circuit monitors the feedback voltages to detect
OC1
OC1
OC2
OC1
OC2
@ DCR
+ I
+ I
+ I
+ I
O1max
O2max
O1max
O2max
I
I
OC1
OC2
1
@ k
Omax
+ I
+ I
)
)
@ 1 )
@ 1 )
CS1
DCR
DCR
O1max
O2max
+ I
per channel.
1
1
I
I
OC2
O1max
O1max
@ k
@ k
TH_OC
DCR
DCR
CS1
CS1
@ DCR
I
I
O2max
O1max
) I
) I
2
1
) DCR
) DCR
= 30 mV, that means
@ k
@ k
O2max
O2max
2
OC
CS2
CS1
@ k
2
2
CS2
is the maximum
@ k
@ k
+ V
CS2
CS2
CC
TH_OC
(eq. 27)
(eq. 28)
(eq. 29)
(eq. 30)
(eq. 31)
(eq. 32)
(eq. 33)
and/or