RS5C313 RICOH Co.,Ltd., RS5C313 Datasheet - Page 25

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RS5C313

Manufacturer Part Number
RS5C313
Description
Ultra-compact Real-time Clock Ic
Manufacturer
RICOH Co.,Ltd.
Datasheet

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11.3 Read Operation from Clock and Calendar Counters
11.3-1
11.3-3
*
Control register ←2h, 6h
Read data as described in 11.3-2 or 11.3-3 when it takes (1/1024) sec or more to set the WTEN bit from 0 to 1 (CE=L),
the read operation described in 11.3-1 is prohibited as such a case.
4
Interrupt to CPU
Read from clock
calendar counter
Control register ←0h, 4h
CTFG=1?
Read from clock and
calendar counters.
BSY=0?
YES
CE=H
CE=L
YES
*
*
7
8
*
NO
6
Interrupt operation
from any other IC
*
*
1
2
NO
operations.
Wait or
CE=L
other
*
3
*
*
*
*
*
*
*
*
Note
1) After switching the CE pin to the high level, hold it at the high level until any
2) Write 0h for the 12-hour format or 4h for the 24-hour time display system.
3) The BSY bit is held at 1 for a maximum duration of 122.1 us.
4) Switch the CE pin to the low level to set the WTEN bit to 1.
5) When needing any higher-order digits than the minute digits, replace second
6) Select the level mode as an interrupt mode by setting the CT3 bit to 1.
7) Write 2h for the 12-hour format or 6h for the 24-hour format.
8)
subsequent operation requires switching it to the low level. (Note that switch-
ing the CE pin to the low level sets the WTEN bit to 1.)
During write operation to the clock and calendar counters, one 1-second digit
carry causes a 1-second increment while two 1-second digit carries also
cause only a 1-second increment, which, in turn, causes a time delay.
digits with minute digits. (Reading LSD one of the required digits twice.)
(e.g. within 1 second).
Complete read operation within an interrupt cycle after interrupt generation
11.3-2
NO
Again read 1-second digit
Read 1-second digit
Read from clock and
calendar counters.
of clock counter.
of clock counter.
digit readings
Two1-second
match?
YES
*
*
*
5
5
5
RS5C313
25

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