HT46R12A Holtek Semiconductor Inc., HT46R12A Datasheet - Page 24

• Manufacturer Part Number: HT46R12A
• Description: Ht46r12a -- A/d Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Note:
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
Start_conversion:
Polling_EOC:
Rev. 1.00
Bit No.
Bit No.
ADRL (24H)
ADRH (25H)
2~6
clr
mov
mov
mov
mov
clr
set
clr
sz
jmp
mov
mov
mov
mov
jmp
0
1
7
0
1
2
3
4
5
6
7
Register
D0~D8 is A/D conversion result data bit LSB~MSB.
ADCS0
ADCS1
START Starts the A/D conversion. (0 1 0= start; 0 1= Reset A/D converter and set EOCB to 1 )
EOCB
Label
Label
ACS0
ACS1
ACS2
PCR0
PCR1
PCR2
TEST
EADI
a,00000001B
ACSR,a
a,00100000B
ADCR,a
:
:
:
START
START
START
EOCB
polling_EOC
a,ADRH
adrh_buffer,a
a,ADRL
adrl_buffer,a
:
:
start_conversion
Selects the A/D converter clock source
00: system clock/2
01: system clock/8
10: system clock/32
11: undefined
Unused bit, read as 0
For test mode used only
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, x, x: Undefined, cannot be used
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption
Indicates end of A/D conversion. (0: end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, other-
wise the EOCB flag may have an undefined condition. See Important note for A/D initialization .
Bit7
D0
D8
Bit6
D7
; disable ADC interrupt
; setup the ACSR register to select f
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
; read conversion result high byte value from the ADRH register
; save result to user defined memory
; read conversion result low byte value from the ADRL register
; save result to user defined memory
; start next A/D conversion
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
ADRL (24H), ADRH (25H) Register
Bit5
ACSR (27H) Register
ADCR (26H) Register
D6
24
Bit4
D5
Function
Function
Bit3
D4
SYS
/8 as the A/D clock
Bit2
D3
Bit1
D2
HT46R12A
August 3, 2007
Bit0
D1