HT46R63 Holtek Semiconductor Inc., HT46R63 Datasheet - Page 13

• Manufacturer Part Number: HT46R63
• Description: Ht46r63/ht46c63 -- A/d With Lcd Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

Watchdog Timer - WDT
The clock source of WDT (and LCD, RTC, Time Base )
is implemented by a dedicated crystal oscillator
(32.768kHz: RTCOSC) or instruction clock (system fre-
quency divided by 4: f
(12kHz:WDTOSC) decided by options. This timer is de-
signed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The watchdog timer can be disabled by options.
If the watchdog timer is disabled, all the executions re-
lated to the WDT result in no operation. The WDT
time-out period is fixed as 2
frequency of WDT, time base, RTC and LCD. If
WDTOSC is selected as the WDT clock, the time-out
period may vary with temperatures, VDD and process
variations. The WDTOSC and RTCOSC can be still run-
ning (decided by option) at the halt mode if they are se-
lected as the WDT clock source. Once the 32.768kHz
oscillator (with a period of 31.25 s normally) is selected
to be the clock source of WDT (and LCD, RTC, Time
Base), it is directly divided by 2
time-out period of 2 seconds. If the WDT clock comes
from the instruction clock, the WDT will stop counting
and lose its protecting purpose in halt mode. In this situ-
ation the logic can only be restarted by external logic. If
the device operates in a noisy environment, using the
RTCOSC or WDTOSC is strongly recommended, since
the HALT will stop the system clock.
The overflow of WDT under normal operation will initial-
ize chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset ,
and only the program counter and SP are reset to zero.
To clear the contents of WDT , 3 methods are adopted;
external reset (a low level to RES), software instruc-
tion(s) and a HALT instruction. The software instruc-
tion(s) include CLR WDT and the other set
WDT1 and CLR WDT2 Of these two types of instruc-
tion, only one can be active depending on the options
selected (i.e. CLRWDT times equal one), any execution
of the CLR WDT instruction will clear the WDT. In the
Rev. 2.30
CLR WDT times selection option . If the CLR WDT is
SYS
/4) or a dedicated RC oscillator
16
/f
S
.
The f
16
to get the nominal
S
means the clock
Watchdog Timer
CLR
13
case that CLR WDT1 and CLR WDT2 are chosen
(i.e. CLR WDT times equal two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out. The RTC os-
cillator should be designed as an auto-speed-up oscilla-
tor. After the RTC oscillator is oscillating, the
auto-speed-up should be turned off.
Time Base Generator
There is a time base generator implemented in the mi-
cro-controller. The time base generator provides
time-out periods selection whose range from f
f
stack is not full and the time base interrupt is enabled,
an interrupt subroutine call to ROM location 010H will
activate.
RTC Generator
There is an RTC generator implemented in the mi-
cro-controller. The RTC generator provides software
configurable real time clock periods whose range from
f
stack is not full and the RTC interrupt is enabled, an in-
terrupt subroutine call to ROM location 018H will acti-
vate. The RTCC is the real time clock control register
used to select the division ratio of RTC clock sources.
RTCC.7~RTCC.3 cannot be used.
S
S
/2
/2
RTCC.2
15
8
to f
0
0
0
0
1
1
1
1
. When the time base time-out occurs and the
S
/2
15
RTCC.1
. When the RTC time-out occurs and the
0
0
1
1
0
0
1
1
RTCC.0
HT46R63/HT46C63
0
1
0
1
0
1
0
1
Divided Factor
RTC Clock
March 22, 2006
2
2
2
2
2
2
2
2
10
11
12
13
14
15
8
9
S
/2
12
to