DSPIC30F2012 Microchip Technology Inc., DSPIC30F2012 Datasheet - Page 199

• Manufacturer Part Number: DSPIC30F2012
• Description: Dspic30f2011/2012/3012/3013 High-performance Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

Timing Specifications
Trap Vectors ....................................................................... 67
U
UART Module
UART Operation
Unit ID Locations............................................................... 119
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ......................................................... 119
Wake-up from Sleep and Idle ............................................. 68
Watchdog Timer
Watchdog Timer (WDT) ............................................ 119, 129
WWW Address.................................................................. 199
WWW, On-Line Support ....................................................... 7
© 2006 Microchip Technology Inc.
Input Capture ............................................................ 165
Oscillator Start-up Timer ........................................... 161
Output Compare Module........................................... 166
Power-up Timer ........................................................ 161
Reset......................................................................... 161
Simple OC/PWM Mode............................................. 167
SPI Module
Type A Timer External Clock .................................... 163
Type B Timer External Clock .................................... 164
Type C Timer External Clock .................................... 164
Watchdog Timer........................................................ 161
PLL Clock.................................................................. 157
Address Detect Mode ............................................... 105
Auto-Baud Support ................................................... 106
Baud Rate Generator................................................ 105
Enabling and Setting Up ........................................... 103
Framing Error (FERR)............................................... 105
Idle Status ................................................................. 105
Loopback Mode ........................................................ 105
Operation During CPU Sleep and Idle Modes .......... 106
Overview ................................................................... 101
Parity Error (PERR) .................................................. 105
Receive Break........................................................... 105
Receive Buffer (UxRXB) ........................................... 104
Receive Buffer Overrun Error (OERR Bit) ................ 104
Receive Interrupt....................................................... 104
Receiving Data.......................................................... 104
Receiving in 8-bit or 9-bit Data Mode........................ 104
Reception Error Handling.......................................... 104
Transmit Break.......................................................... 104
Transmit Buffer (UxTXB)........................................... 103
Transmit Interrupt...................................................... 104
Transmitting Data...................................................... 103
Transmitting in 8-bit Data Mode................................ 103
Transmitting in 9-bit Data Mode................................ 103
UART1 Register Map................................................ 107
UART2 Register Map................................................ 107
Idle Mode .................................................................. 106
Sleep Mode............................................................... 106
(UART) Module ......................................................... 101
Timing Characteristics .............................................. 161
Timing Requirements................................................ 161
Enabling and Disabling ............................................. 129
Operation .................................................................. 129
Master Mode (CKE = 0) .................................... 168
Master Mode (CKE = 1) .................................... 169
Slave Mode (CKE = 0) ...................................... 170
Slave Mode (CKE = 1) ...................................... 172
dsPIC30F2011/2012/3012/3013
DS70139E-page 197