PR31500 NXP Semiconductors, PR31500 Datasheet - Page 21

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PR31500

Manufacturer Part Number
PR31500
Description
Poseidon Embedded Processor
Manufacturer
NXP Semiconductors
Datasheet
Values shown assume a 40MHz clock for the CPU, MIN and MAX values are programmable using Video Control Registers.
Philips Semiconductors
VIDEO
T
NOTE:
VIDEO TIMING DIAGRAMS
1996 Sep 24
amb
Poseidon embedded processor
ITEM
ITEM
= 0 to +70 C, V
1
2
3
4
5
6
7
LOAD Pulse width
Delay LOAD Falling to FRAME
Delay LOAD Falling to DF
Delay LOAD Falling to CP
Delay CP Rising to VDAT[3:0]
VDAT to CP Rising Setup
VDAT to CP Rising Hold
VDAT[3:0]
VDAT[3:0]
DD
FRAME
LOAD
= 3.3
CP
CP
DF
0.3V, External Capacitance = 40pF
Figure 13. Video Data Timing, 4 Bit Split LCD and 8 Bit Non-Split LCD
PARAMETER
PARAMETER
Figure 12. Video Timing, 4 Bit Non-Split LCD
1
6
21
7
2
3
4
RISING/FALLING
RISING/FALLING
5
MIN
100
100
100
100
15
15
LIMITS
Preliminary specification
MAX
1600
3200
3200
3200
25
25
3
PR31500
MIPS
UNIT
UNIT
SN00179
SN00180
ns
ns
ns
ns
ns
ns
ns

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