MC74LVX541MELG ON Semiconductor, MC74LVX541MELG Datasheet

MC74LVX541MELG

Manufacturer Part Number

MC74LVX541MELG

Description

IC BUFF/DVR 8BIT N-INV 20SOEIAJ

Manufacturer

ON Semiconductor

Series

74LVXr

Datasheet

1.MC74LVX541DTR2G.pdf (8 pages)

Specifications of MC74LVX541MELG

Logic Type

Buffer/Line Driver, Non-Inverting

Number Of Elements

Number Of Bits Per Element

Current - Output High, Low

4mA, 4mA

Voltage - Supply

2 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ

Logic Family

LVX

Number Of Channels Per Chip

Polarity

Non-Inverting

Supply Voltage (max)

3.6 V

Supply Voltage (min)

2 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

High Level Output Current

- 4 mA

Low Level Output Current

4 mA

Maximum Power Dissipation

500 mW

Minimum Operating Temperature

- 40 C

Number Of Lines (input / Output)

8 / 8

Output Type

3-State

Propagation Delay Time

10.5 ns at 2.7 V, 7 ns at 3.3 V

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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MC74LVX541

Octal Bus Buffer

buffer fabricated with silicon gate CMOS technology. It achieves high

speed operation similar to equivalent Bipolar Schottky TTL while

maintaining CMOS low power dissipation.

are high, the terminal outputs are in the high impedance state.

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

February, 2010 − Rev. 3

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC74LVX541 is an advanced high speed CMOS octal bus

The MC74LVX541 is a noninverting type. When either OE1 or OE2

The internal circuit is composed of three stages, including a buffer

High Speed: t

Low Power Dissipation: I

High Noise Immunity: V

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Designed for 2 V to 3.6 V Operating Range

Low Noise: V

Pin and Function Compatible with Other Standard Logic Families

Latchup Performance Exceeds 300 mA

Chip Complexity: 134 FETs or 33.5 Equivalent Gates

ESD Performance:

Pb−Free Packages are Available*

Human Body Model > 2000 V;

Machine Model > 200 V

OLP

= 5.0 ns (Typ) at V

= 1.2 V (Max)

NIH

= 4 mA (Max) at T

= V

NIL

= 28% V

= 3.3 V

= 25°C

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

(Note: Microdot may be in either location)

ORDERING INFORMATION

L, WL

Y, YY

W, WW

G or G

http://onsemi.com

CASE 948E

DT SUFFIX

SOEIAJ−20

TSSOP−20

M SUFFIX

CASE 967

DW SUFFIX

CASE 751D

SOIC−20

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Publication Order Number:

DIAGRAMS

AWLYWWG

AWLYYWWG

MARKING

MC74LVX541/D

LVX541

ALYWG

LVX541

LVX

541

Related parts for MC74LVX541MELG

MC74LVX541MELG Summary of contents

Page 1

... Human Body Model > 2000 V; Machine Model > 200 V • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2010 February, 2010 − Rev 3 25° ...

Page 2

DATA INPUTS OE1 OUTPUT ENABLES 19 OE2 Figure 1. LOGIC DIAGRAM OE1 OE2 ...

Page 3

MAXIMUM RATINGS Symbol Parameter V DC Supply Voltage Input Voltage Output Voltage out I Input Diode Current IK I Output Diode Current Output Current, per Pin out I DC Supply Current, ...

Page 4

AC ELECTRICAL CHARACTERISTICS Symbol Parameter t , Maximum Propagation Delay, PLH PHL t , Output Enable TIme, PZL PZH t , Output Disable Time, PLZ PHZ t , ...

Page 5

... ORDERING INFORMATION Device MC74LVX541DWG MC74LVX541DTR2 MC74LVX541DTR2G MC74LVX541M MC74LVX541MG MC74LVX541MEL MC74LVX541MELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. TEST CIRCUITS OUTPUT DEVICE UNDER ...

Page 6

20X 0. 18X A1 T PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G NOTES DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET ...

Page 7

K 20X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT 1 0.15 (0.006 −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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