EM566168 Etron Technology Inc., EM566168 Datasheet
EM566168
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EM566168 Summary of contents
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... SS Overview The EM566168 is a 16M-bit Pseudo SRAM organized as 1M words by 16 bits designed with advanced CMOS technology specified RAM featuring low power static RAM compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power ...
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... Buffer DQ0 – DQ7 DQ8 – DQ15 CS1# CS2 OE# Control Logic WE# LB# UB# Preliminary Standby/Deep Power Down Mode Control Memory Cell Array Row Address Decoder Input Sense AMP Data Control Column Decoder Address Buffer 2 Rev 0.2 EM566168 Output Data Control Feb. 2002 ...
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... Upper Byte Write L D-in D-in Word Write 1) -0.2 to +3.6V -0.2 to VCC + 0.3V -2.0 to +3.6V* 100 mA -25 to +85°C -65 to +125°C 240° Min. Typ. 2.7 3.0 0 2.2 2) -0.2 3 EM566168 Mode Power Standby Deep Power Down Standby Active Active Active Active Active Active Active Active Max. Unit 3 − 1) − ...
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... Other inputs = CE2 ≤ 0.2V, Other inputs = 2.1mA -1.0mA Min Typ Max Unit Test Conditions 8 pF − − OUT = GND − − 4 EM566168 Min. Max. Unit -1 1 µ µ − − 100 µA − 10 µ ...
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... Write Cycle 85 − 60 − 70 − 70 − 70 − 0 − 0 − 30 − 5 − 30 − 0 − 5 Rev 0.2 EM566168 -70 Unit Min Max 70 ns − − − − − − − − − − ...
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... Deep Power Down Exit CE1# = VIH or VIL, CE2=VIH CE2=VIL Active CE2=VIH, CE1# =VIH or UB#, LB# =VIH CE1# =VIL, CE2=VIH, UB# & LB# or/and LB# = VIL Standby Current (µA) Valid 100 Invalid 10 6 EM566168 Deep Power Down Mode CE2=VIL Standby Mode Wait Time (µs) 0 200 Rev 0.2 Feb. 2002 ...
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... UB#, LB# OE# High-Z Data Out Notes: 1. CE1 CE2 = WE CE2 = WE Preliminary 1) tRC tAA tOH tOH 2) tRC tAA tCO tLZ tBA tBLZ tOE tOLZ Data Valid , UB# or/and LB EM566168 Data Valid tOH tHZ tBHZ tOHZ High-Z Rev 0.2 Feb. 2002 ...
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... Write Cycle 2 – CS1# Controlled Address CE1# UB#, LB# WE# Data In High-Z Data Out Preliminary 1) 2) tWC tAW tCW tBW tWP tAS tDW Data Valid tWHZ 1) 2) tWC tAW tAS tCW tBW tWP tDW Data Valid 8 EM566168 tWR tDH High-Z tOW tWR tDH Rev 0.2 Feb. 2002 ...
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... Et ronTech Write Cycle 3 – UB#, LB# Controlled Address CE1# UB#, LB# WE# Data In High-Z Data Out Notes: 1. CE2 = CE2 = WE Preliminary 1) 2) tWC tAW tCW tBW tAS tWP tDW Data Valid 9 EM566168 tWR tDH Rev 0.2 Feb. 2002 ...
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... CE1# Power Up 2 (No Dummy Cycle CE2 CE1# Preliminary 200µs 1µs Wake Up Deep Power Suspend Down Mode Read Operation Tiwce 200µs 200µs 300µs 10 EM566168 Read Operation Twice or Stay High during 300µs Normal Operation Rev 0.2 Feb. 2002 ...
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... Avoidable timing 1 or toggle CE1# to high ( one time at least shown as in Avoidable Timing 2. Abnormal Timing CE1# WE# Address Avoidable Timing 1 CE1# WE# Address Avoidable Timing 2 CE1# WE# Address Preliminary 15µs < tRC 15µs tRC 15µs < tRC 11 Rev 0.2 EM566168 tRC) tRC Feb. 2002 ...
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... Units Preliminary EM566168 0 0 ...