SSD2119 Crystalfontz America, Inc.,, SSD2119 Datasheet
SSD2119
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SSD2119 Summary of contents
Page 1
... RGB x 240 TFT LCD Driver Integrated Power Circuit, Source and Gate Driver and RAM This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com Rev 1.4 P 1/95 SSD2119 SSD2119 Advance Information Copyright © 2009 Solomon Systech Limited Jun 2009 ...
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... P.70 Updated RGB Timing Characteristics 0.45 P.62 Updated Gama Ladder Resistor table format P.12-22, 36, 59-60, 80, 84 Fixed format of Table 5-2, TB Table, Grayscale Amplifier, Power supply block diagram and Figure 19-4 Solomon Systech IC Revision history of SSD2119 Specification (8 color) on page 13 dp 1001 9-bit 6800 1010 18-bit 8080 1011 9-bit 8080 ...
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... P.57 Add Program voltage range – 14.5 to 15.5 P.57 Added “It is possible to skip step3 and step4” and changed “Step 4-9” to “Step 5-9” P.34, 54 Added R20h Uniformity settings 1.1 P.11 Updated ordering part number as SSD2119Z7 P.73 Removed (/CS) from tr and tf P.73 Added VCI and Reset pin to diagram P.74 Removed (/CS) from tr and tf P.75 Added VCI and Reset pin to diagram P ...
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... Version Change Items P.96 Added Chiptray diagram of SSD2119Z7 P.95 Corrected shifted VCHS to Gnd wire to proper position P.47 Added notes below table of R0CH 1.2 P.52 Added “Note: ID and AM functions are not supported in RGB mode” P.50 Added “DenMode=1 (DEN signal is necessary); DenMode=0 (DEN pin must connect to VDDIO)” ...
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... AC CHARACTERISTICS......................................................................................................................................13 14 GDDRAM ADDRESS ...........................................................................................................................................13 15 INTERFACE MAPPING........................................................................................................................................13 15 ............................................................................................................................................13 NTERFACE ETTING 15.1.1 6800-series System Bus Interface ...............................................................................................................13 15.1.2 8080-series System Bus Interface ...............................................................................................................13 15 APPING FOR RITING AN Rev 1.4 P 5/95 SSD2119 RAM (GDDRAM) ......................................................................................................13 G .....................................................................................................13 ENERATOR C ...................................................................................................................13 IRCUIT C ......................................................................................................................13 IRCUIT A ..............................................................................................................13 MPLIFIER ........................................................................................................................13 EGISTER ........................................................................................................................13 EGISTER 1 .................................................................................................................13 SELECTOR I ...........................................................................................................13 ...
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... ALT EQUENCE 16 LEEP ODE ISPLAY 16 EEP LEEP ODE ISPLAY 17 POWER SUPPLY BLOCK DIAGRAM ................................................................................................................13 18 SSD2119 OUTPUT VOLTAGE RELATIONSHIP ...............................................................................................13 19 APPLICATION CIRCUIT .....................................................................................................................................13 20 PACKAGE INFORMATION.................................................................................................................................13 20 HIP RAY NFORMATION 21 OTP DETAIL .........................................................................................................................................................13 Solomon Systech P D ...................................................................................................................13 IXEL ATA P D ......................................................................................13 ...
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... TABLES C T 13-1: RGB T ORRECTED ABLE IMING P. 13-2: RGB T ORRECTED ABLE T 3- ABLE RDERING NFORMATION T 5- ABLE IE NFORMATION T 5-2: SSD2119 ABLE UMP 6- .........................................................................................................................................13 ABLE OWER UPPLY INS T 6- ABLE NTERFACE OGIC INS T 6- ABLE ODE ELECTION INS T 6- ...
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... FIGURES F 4-1: SSD2119 B D IGURE LOCK IAGRAM F 5-1: SSD2119 IGURE IE AD LOOR F 5- ........................................................................................................................................13 IGURE LIGNMENT ARKS F 5- IGURE UTPUT AD ITCH F 7- IGURE EAD ISPLAY ATA F 7-2: 4- SPI IGURE WIRE INTERFACE F 7-3: 3- SPI IGURE WIRE INTERFACE F 9-1: IGURE GATE OUTPUT TIMING IN ...
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... GENERAL DESCRIPTION SSD2119 is an all in one TFT LCD Driver that integrated the power circuits, gate driver and source driver into a single chip. It can drive up to 262k color amorphous TFT panel with resolution of 320 RGB x 240. It also integrated the controller function and consists 172,800 bytes (320 x 240 Graphic Display Data RAM (GDDRAM) such that it interfaced with common MCU through 8/9/16/18-bits 6800- series / 8080-series compatible Parallel Interface or Serial Interface and stored the data in the GDDRAM ...
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... Support source and gate scan direction control • Programmable gamma correction curve • 4 Preset gamma correction curve • Built-in Non Volatile Memory for VCOM calibration • Support flexible arrangement of gate circuits on both sides of the glass substrate Solomon Systech Jun 2009 P 10/95 Rev 1.4 SSD2119 ...
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... ORDERING INFORMATION Source Ordering Part Number output channel 320 x 3 SSD2119Z7 (960) Rev 1.4 P 11/95 SSD2119 Table 3-1: Ordering Information Gate output Package Form channel 240 Gold Bump Die Jun 2009 Reference Remark Solomon Systech ...
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... VCIP C1N C1P C2N Booster C2P C3N Circuit C3P CXP CXN CYP CYN OSC VSS/AVSS/ VCHS/VSSRC Solomon Systech Figure 4-1: SSD2119 Block Diagram G1 to G240 VCOM Regulator Circuit Gamma / Grayscale Voltage Generator Regulator Circuit VLCD63 VGH VGL GateDriver Timing Generation System Interface ...
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... DIE PAD FLOOR PLAN Figure 5-1: SSD2119 Die Pad Floor Plan Pin 1 Pin 360 Rev 1.4 P 13/95 SSD2119 Pin 1574 Die Size (no scribe) Die Thickness Typical Bump Height 15 um Bump Co-planarity (within die) Bump Size 1 Pad Pitch 1 Bump Size 2 Pad Pitch 2 Pin 361 Jun 2009 ...
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... Table 5-2: SSD2119 Bump Die Pad Coordinates (Bump Centre) Note: IC material temperature expansion factor is 2.6ppm, customer should take into account during panel design Pad # Pad Name X-pos Y-pos VCOM -10770 1 VCOM -10710 2 3 VCOM -10650 VCOM -10590 4 VCOM -10530 5 VCOM -10470 6 VCOM ...
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... CDUM0 990 -286 197 EXVR 1050 -286 198 199 VCOMR 1110 -286 VLCD63 1170 -286 200 Rev 1.4 P 15/95 SSD2119 Pad # Pad Name X-pos Y-pos Pad # DUMMY 1230 -286 201 DUMMY 1290 -286 202 DUMMY 1350 -286 203 DUMMY 1410 -286 ...
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... G161 9501 226 441 G163 9483 81 442 G165 9465 226 443 G167 9447 81 444 G169 9429 226 445 446 G171 9411 81 G173 9393 226 447 G175 9375 81 448 449 G177 9357 226 G179 9339 81 450 Jun 2009 P 16/95 Rev 1.4 SSD2119 ...
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... S14 8497 81 496 S15 8479 226 497 498 S16 8461 81 S17 8443 226 499 S18 8425 81 500 Rev 1.4 P 17/95 SSD2119 Pad # Pad Name X-pos Y-pos Pad # S19 8407 226 501 S20 8389 81 502 S21 8371 226 503 S22 8353 81 504 S23 ...
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... S259 4087 226 741 S260 4069 81 742 S261 4051 226 743 S262 4033 81 744 S263 4015 226 745 746 S264 3997 81 S265 3979 226 747 S266 3961 81 748 749 S267 3943 226 S268 3925 81 750 Jun 2009 P 18/95 Rev 1.4 SSD2119 ...
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... S314 3097 81 796 S315 3079 226 797 798 S316 3061 81 S317 3043 226 799 S318 3025 81 800 Rev 1.4 P 19/95 SSD2119 Pad # Pad Name X-pos Y-pos Pad # S319 3007 226 801 S320 2989 81 802 S321 2971 226 803 S322 2953 81 804 S323 ...
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... S549 -1333 226 1041 S550 -1351 81 1042 S551 -1369 226 1043 S552 -1387 81 1044 S553 -1405 226 1045 1046 S554 -1423 81 S555 -1441 226 1047 S556 -1459 81 1048 1049 S557 -1477 226 S558 -1495 81 1050 Jun 2009 P 20/95 Rev 1.4 SSD2119 ...
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... S604 -2323 81 1096 S605 -2341 226 1097 1098 S606 -2359 81 S607 -2377 226 1099 S608 -2395 81 1100 Rev 1.4 P 21/95 SSD2119 Pad # Pad Name X-pos Y-pos Pad # S609 -2413 226 1101 1151 S610 -2431 81 1102 1152 S611 -2449 226 1103 1153 S612 -2467 ...
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... S849 -6733 226 1341 S850 -6751 81 1342 1343 S851 -6769 226 S852 -6787 81 1344 S853 -6805 226 1345 S854 -6823 81 1346 S855 -6841 226 1347 S856 -6859 81 1348 S857 -6877 226 1349 S858 -6895 81 1350 Jun 2009 P 22/95 Rev 1.4 SSD2119 ...
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... S904 -7723 81 1396 S905 -7741 226 1397 1398 S906 -7759 81 S907 -7777 226 1399 S908 -7795 81 1400 Rev 1.4 P 23/95 SSD2119 Pad # Pad Name X-pos Y-pos Pad # S909 -7813 226 1401 1451 S910 -7831 81 1402 1452 S911 -7849 226 1403 1453 S912 -7867 ...
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... G6 -10905 1572 226 G4 -10923 1573 81 G2 -10941 1574 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 Y-pos 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 226 81 Jun 2009 P 24/95 Rev 1.4 SSD2119 ...
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... C1N C2P Booster capacitor C2N C3P Booster capacitor C3N Rev 1.4 P 25/95 SSD2119 Table 6-1: Power Supply Pins Function System ground pin of the IC. Ground of Grounding for gamma circuit the Power Grounding for analog circuit. Supply Grounding for booster circuit. Booster input voltage pin. Power - Connect to voltage source between 2 ...
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... Vdd for core use. Connect a capacitor for stabilization Core Logic Regulator output for Regulator output for VCORE use. logic circuits Power for Voltage input pin for logic I/O, connect to system VDD. interface - Connect to voltage source between 1.4V to 3.6V logic pins Description Jun 2009 P 26/95 Rev 1.4 SSD2119 When not in use Open - - - ...
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... SDI I MPU SDO O MPU SCL I MPU Rev 1.4 P 27/95 SSD2119 Table 6-2: Interface Logic Pins Function Data or command DC : Parallel Interface SDC : Serial Interface CS : Chip select pin for 6800/8080 Parallel Interface SCS : Chip Select pin for Serial Mode Interface Logic 6800-system : E (enable signal) Control 8080-system : RD (read strobe signal) ...
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... SPI 1 4-wire SPI Description , GOFFH Description Jun 2009 P 28/95 Rev 1.4 When not in use - When not in use Open Open Open When not in use Open Open SSD2119 ...
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... GDDRAM or writing the command to the command register is controlled by DC. A dummy read is also required before the first actual display data read for 8080-series interface. Please refer to . Rev 1.4 P 29/95 SSD2119 Table 7-1: Data bus selection modes 8080 – series Parallel Interface Interface ...
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... Transfer starts SCS SDC SCL 7 8 SDI Transfer ends 7 8 Jun 2009 P 30/95 Transfer starts Transfer ends LSB MSB Data Frame 2 (Data 5Ah) Transfer ends Rev 1.4 SSD2119 ...
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... Transfer starts SCS SCL SDI Frame 3 (Data 78h) Transfer starts SCS SCL SDI Rev 1.4 P 31/95 SSD2119 : 3-wire SPI interface (9 bits) Figure 7-3 Transfer starts Transfer ends LSB MSB ...
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... RGB Interface SSD2119 supports RGB interface. RGB interface unit consists of D[17:0], HSYNC, VSYNC, DOTCLK and DEN signals for display moving pictures. When the RGB interface is selected, the display operation is synchronized with external control signals (HSYNC, VSYNC and DOTCLK). Data is written in synchronization with the control signals when DEN is enabled for write operation in order to avoid flicker or tearing effect while updating display data ...
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... Liquid Crystal Driver Circuit SSD2119 consists of a 960-output source driver (S1-S960) and a 240-output gate driver (G1-G240). The display image data is latched when 960 bits of data are inputted. The latched data control the source driver and output drive waveforms. The gate driver for scanning gate lines outputs either VGH or VGL level. ...
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... VRH3 VRH2 VRH1 VRH0 SCN3 SCN2 SCN1 SCN0 SLP INVVS HBP3 HBP2 HBP1 HBP0 VBP3 VBP2 VBP1 VBP0 SSD2119 ...
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... R4Eh (0000h) Set GDDRAM address counter R4Fh (0000h) Note: In R01h, bits REV, BGR, RL, CM will override the corresponding hardware pins settings. Setting R28h as 0x0006 is required before setting R25h and R29h registers. Rev 1.4 P 35/95 SSD2119 ...
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... IB6 IB5 IB4 IB3 IB2 Vcom = ”H” V63 V63 : V0 Right Side G240, 218, … G239, 317, … Jun 2009 P 36/95 Rev 1.4 IB1 IB0 ID1 ID0 IB1 IB0 0 1 IB1 IB0 0 OSCEN 0 0 IB1 IB0 1 1 SSD2119 ...
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... Remark: When using the partial display, the output for non-display area will be minimum voltage. TB When scan from G1 to G240 When scan from G240 to G1 Rev 1.4 P 37/95 SSD2119 Gate scan squence (GD=’0’) G1, G2, G3……G240 (left and right gate interlaced) G1, G3, ……G239, G2, G4, ……G240 Jun 2009 Solomon Systech ...
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... G237 G239 G238 G240 S960 G237 G239 G238 G240 S960 G237 G239 G238 G240 S960 S960 S1 S960 S1 S1 S960 S960 S1 Jun 2009 P 38/95 Rev 1.4 SSD2119 G2 G4 G238 G240 G2 G4 G238 G240 G2 G4 G238 G240 G2 G4 G238 G240 ...
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... G237 G239 G237 G239 G237 G239 G237 G239 S1 Rev 1.4 P 39/95 SSD2119 G238 G240 G237 G239 S960 G238 G240 G237 G239 S960 G238 G240 ...
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... frame Blank period Field 1 Field 2 Field 3 IB7 IB6 IB5 IB4 IB3 IB2 NW6 NW5 NW4 NW3 NW2 NW1 NW0 FLD = 0 FLD = Field 1 Jun 2009 P 40/95 Rev 1.4 IB1 IB0 SSD2119 ...
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... NW[7:0]: Specify the number of lines that will alternate at the N-line inversion setting (B/C = 1). N-line is equal to NW[7:0]+1. Back porch Frame Inversion 320 line drive Back porch Line Inversion 320 line drive Rev 1.4 P 41/95 SSD2119 Figure 9-2: Line Inversion AC Driver N Frame Front porch Back porch 242 255 256 1 N Frame Front porch Back porch 242 255 256 1 ...
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... Fast write MCU Slow write MCU SSD2119 displaying memory tn is the time when there is No Update of LCD screen from on-chip ram content the time when the LCD screen is updating based on on-chip ram content. e.g. fosc = 380KHz, for 320mux 282us (6 lines), tu =15.06ms (320 lines) ...
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... BT2 BT1 BT0 Rev 1.4 P 43/95 SSD2119 IB10 IB9 IB8 IB7 BT1 BT0 0 DC3 DCT3 DCT2 DCT1 DCT0 Step-up cycle Fline × Fline × Fline × ...
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... Fline = Line frequency fosc = Internal oscillator frequency (~380KHz) AP2 AP1 AP0 Op-amp power Least Small Small to medium Medium Medium to large Large Large to Maximum Maximum ). When the cycle is accelerated, the SS Jun 2009 P 44/95 Rev 1.4 SSD2119 ...
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... Frame Cycle Control (R0Bh) (POR = 5308h) R/W DC IB15 IB14 IB13 IB12 W 1 NO1 NO0 SDT1 SDT0 POR NO[1:0]: Sets amount of non-overlap of the gate output. Gn Gn+1 Rev 1.4 P 45/95 SSD2119 IB10 IB9 IB8 IB7 PT0 VLE2 VLE1 SPT Internal Display Source output Operation Halt GND Operation ...
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... Delay amount of the source output DIV1 DIV0 Division Ratio fosc = internal oscillator frequency, ~380kHz EQ period clock cycle 3 clock cycle 4 clock cycle 5 clock cycle 6 clock cycle 7 clock cycle 8 clock cycle Equalizing period Jun 2009 P 46/95 Rev 1.4 SSD2119 ...
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... For DMode = ‘0’ _ Frame where Fosc = internal oscillator frequency div = Division ratio determined by DIV[1:0] rtn = RTN[3:0] mux = MUX[8:0] vbp = VBP[7:0] vfp = VFT[7:0] for default values of SSD2119 Fosc = ~380KHz, DIV[1:0] = ‘00’, RTN[3: MUX[8:0] = 239, VBP[7: VFP[7: 380 Frame frequency = × + × ...
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... IB6 IB5 IB4 IB3 IB2 Vcom Amplitude VLCD63 x 0.60 VLCD63 x 0.63 VLCD63 x 0.66 : Step = 0.03 : VLCD63 x 0.99 VLCD63 x 1.02 Reference from external variable resistor VLCD63 x 1.05 VLCD63 x 1.08 : Step = 0.03 : VLCD63 x 1.20 VLCD63 x 1.23 Reserved Reserved Jun 2009 P 48/95 Rev 1.4 IB1 IB0 0 1 IB1 IB0 SSD2119 ...
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... R07, x0000 (display off) Deep sleep mode command R28, x0006 (enable test command) R10, x0001 (enter sleep mode) R12, x2999 (enable deep sleep function) R07, x0000 (display off) VSH[2:0]: Vcore voltage select Rev 1.4 P 49/95 SSD2119 IB10 IB9 IB8 IB7 IB6 SCN8 SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 ...
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... The display operation is performed in synchronization with the internal clock signal generated from the internal oscillator and the VSYNC signal. The display data is written in the internal RAM so that the SSD2119 rewrites the data only within the moving picture area and minimize the number of data transfer required for moving picture display. ...
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... bit 262k Type 262k Type Remark : x Rev 1.4 P 51/95 SSD2119 TY1 TY0 Writing mode 0 0 Type Type Type C Hardware pins ...
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... IB7 IB6 IB5 IB4 IB3 ID[1:0]="11” Horizontal: increment Vertical: increment 00,00h 13F,EFh 13F,EFh 00,00h 13F,EFh 13F,EFh IB2 IB1 0 0 INVDOT INVDEN INVHS INVVS Jun 2009 P 52/95 Rev 1.4 SSD2119 IB0 0 ...
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... Set by HBP7-0 HYSNC Pixel Dummy Data DOTCLK 30 clock cycles of DOTCLK HBP7-0 = 00011101 Rev 1.4 P 53/95 SSD2119 IB10 IB9 IB8 IB7 IB6 HBP7 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 HBP5 HBP4 HBP3 HBP2 ...
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... Set by MUX[8: Line IB6 IB5 IB4 IB3 IB2 HSYNC 1 (POR Step = 1 : 127 128 No. of clock cycle of HSYNC (POR) : Step = 255 1 256 Set by VFP[6:0] Last Line Dummy Lines Jun 2009 P 54/95 Rev 1.4 IB1 IB0 1 1 SSD2119 ...
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... WD[17:0]: Transforms all the GDDRAM data into 18-bit, and writes the data. Format for transforming data into 18-bit depends on the interface used. SSD2119 selects the grayscale level according to the GDDRAM data. After writing data to GDDRAM, address is automatically updated according to AM bit and ID bit. Access to GDDRAM during stand-by ...
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... Vpp=14.5V-15.0V IB6 IB5 IB4 IB3 IB2 IB1 IB7 IB6 IB5 IB4 IB3 IB2 supply to VGH through Jun 2009 P 56/95 Rev 1.4 IB0 IB1 IB0 SSD2119 ...
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... PKN[52:00]: Gamma micro adjustment register for the negative polarity output PRN[12:00]: Gradient adjustment register for the negative polarity output VRN[14:00]: Adjustment register for the amplification adjustment of the negative polarity output. (For details, see the Section 11 Gamma Adjustment Function). Rev 1.4 P 57/95 SSD2119 Figure 9-3: OTP circuitry ...
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... IB6 IB5 IB4 IB3 IB2 IB7 IB6 IB5 IB4 IB3 IB2 Jun 2009 P 58/95 Rev 1.4 IB1 IB0 240 IB0 0 IB1 IB0 IB1 IB0 SSD2119 ...
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... RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables the SSD2119 to write data including image data sequentially without taking the data wrap position into account. The window address area must be made within the GDDRAM address map area. ...
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... VSA[7:0] = 8Bh; VEA[7:0] = B3h AM = “0” and ID[1;]] = “11” Partial Display Mode The SSD2119 enables to selectively drive two screens at arbitrary positions with the screen-driving position registers (R48h to R4Bh). Only the lines required to display two screens at arbitrary positions are selectively driven to reduce the power consumption. ...
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... GAMMA ADJUSTMENT FUNCTION The SSD2119 incorporates gamma adjustment function for the 262,144-color display. Gamma adjustment is implemented by deciding the 8-grayscale levels with angle adjustment and micro adjustment register. Also, angle adjustment and micro adjustment is fixed for each of the internal positive and negative polarity. Set up by the liquid crystal panel’ ...
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... Individual ladder resistors are used for positive and negative polarity. Amplitude adjustment register PKP5 VRP0 VRP1 VINP0 VINP1 VINP2 VINP3 VINP4 VINP5 VINP6 selector VINP7 Jun 2009 P 62/95 Rev 1 V19 V20 : V42 V43 : V54 V55 : V61 V62 V63 SSD2119 ...
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... RP40 KVP44 RP41 4R KVP45 RP42 KVP46 RP43 KVP47 RP44 KVP48 RP45 10.2 5R RP46 0 to 31R VRP1[4:0] VRP1 8R RP47 GND Rev 1.4 P 63/95 SSD2119 VINP0 VRN0 PKP0[2: VINP1 selector PKP1[2: 28R VRHN VINP2 selector PKP2[2: VINP3 selector PKP3[2:0] ...
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... Also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors. Solomon Systech Amplitude adjustment Grayscale Number Jun 2009 P 64/95 Micro adjustment Grayscale Number Rev 1.4 SSD2119 ...
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... V20+(V8-V20)*(14/24) V14 V20+(V8-V20)*(12/24) V15 V20+(V8-V20)*(10/24) V16 V20+(V8-V20)*(8/24) V17 V20+(V8-V20)*(6/24) V18 V20+(V8-V20)*(4/24) V19 V20+(V8-V20)*(2/24) V20 VINP(N)3 V21 V43+(V20-V43)*(22/23) Rev 1.4 P 65/95 SSD2119 VRP(N)0 Resistance 0000 0R 0001 2R 0010 4R : Step = 2R : 1110 28R 1111 30R Registor VINP4 VINP5 VINP6 ...
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... PKP4[2:0] = “100” PKP4[2:0] = “101” PKP4[2:0] = “110” PKP4[2:0] = “111” PKP5[2:0] = “000” PKP5[2:0] = “001” PKP5[2:0] = “010” PKP5[2:0] = “011” VINP6 PKP5[2:0] = “100” PKP5[2:0] = “101” PKP5[2:0] = “110” PKP5[2:0] = “111” -- VINP7 Jun 2009 P 66/95 Rev 1.4 SSD2119 ...
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... KVN48 VLCD63 - ΔV x (VRN0 + 120R + VRHN + VRLN) / SUMRN KVN49 SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1 ΔV: Voltage difference between VLCD63 and of GND. Rev 1.4 P 67/95 SSD2119 Formula Micr0-adjusting rgister Jun 2009 Reference voltage -- VINN0 PKN0[2:0] = “000” ...
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... SS DDIO A Min Typ Max 1.4 - 3.6 2.5 or VDDIO - 3.6 whichever is higher - 0 +0 CIM - - 0.9* VDDIO - VDDIO 0 - 0.1*VDDIO V 0.8*VDDIO - VDDIO 0 - 0.2*VDDIO - Jun 2009 P 68/95 Rev 1.4 SSD2119 Unit μA μA μA μA ...
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... Ihalt is the current consumption of Power on and Reset keeps low state; the maximum rating is 100uA. The setting of VLCD63 is needed to below 0.5V of VCIX2 the prevention of VCIX2 noise to couple to VLCD63 gamma voltage. Rev 1.4 P 69/95 SSD2119 Vddio= 1.8V, Vci = 2.8V, Ivdd 5x/-5x(VGH/VGL) booster ratio. Full color current consumption, ...
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... PW CSH t DSW 0.8V DDIO Valid Data 0.2V DDIO t ACC 0.7V 0.3V Min Typ Max 450 - - 250 - - 100 - - 500 - - 500 - - - - CSL t DHW t OH DDIO Valid Data DDIO Jun 2009 P 70/95 Rev 1.4 SSD2119 Unit ...
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... Pulse width /CS high (write cycle) CSH PW Pulse width /CS low (read cycle) CSL PW Pulse width /CS high (read cycle) CSH t Rise time R t Fall time F Note: CS can be pulled low during the write cycle, only /RW is needed to be toggled Rev 1.4 P 71/95 SSD2119 ) and and and CS R ...
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... PW t 0.2V AS2 DDIO t DSW 0.8V DDIO 0.2V DDIO 0.8V DDIO 0.2V DDIO t AS1 0.8V DDIO t F 0.2V DDIO 0.8V DDIO PW CSL 0.2V t DDIO AS2 t ACC t AH1 cycle PW t CSH CSL AH2 t DHW Valid Data t AH1 cycle t AH2 PW CSH t OH 0.7V DDIO Valid Data 0.3V DDIO Jun 2009 P 72/95 Rev 1.4 SSD2119 ...
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... Rise time R t Fall time F Figure 13-3: 4 wire Serial Timing Characteristics SDC SCS 0.8V DDIO SCL t F 0.8V SDI 0.2V SCS SCL SDI D7 D6 Rev 1.4 P 73/95 SSD2119 Table 13-3: Serial Timing Characteristics 0.8V DDIO 0.2V DDIO CSS t cycle t CLKL 0.2V DDIO t DSW DDIO Valid Data DDIO Jun 2009 ...
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... DOTCLK High Period CKH t Data Setup Time DS t Data hold Time DH Note: External clock source must be provided to DOTCLK pin of SSD2119. The driver will not operate in absence of the clocking signal. VSYNC HSYNC DOTCLK Pixel DATA Data Solomon Systech Table 13-4: RGB Timing Characteristics ...
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... Figure 13-5: Rev 1.4 P 75/95 SSD2119 Power Up Sequence for RGB mode Jun 2009 Solomon Systech ...
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... V = 1.4V to 3.3V) A DDIO Symbol Parameter t Reset pulse duration RES RESB Solomon Systech Table 13-5: Reset Timing Figure 13-6: Reset Timing Characteristics tRES 0.2VDDIO Min Typ Max Jun 2009 P 76/95 Rev 1.4 SSD2119 Uni t us ...
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... G2 013DH, 0000H G238 G1 013EH, 0000H G239 G0 013FH, 0000H Horizontal address 0 Remark : The address is in 00xxH,0yyyH format, where yyy is the vertical address and xx is the horizontal address Rev 1.4 P 77/95 SSD2119 … S954 S955 S956 S957 S958 S959 … ...
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... Read 8-bit parameters or status* Write 8-bit command Write 8-bit display data Read 8-bit command Read 18-bit parameters or status* Write 8-bit command Write 18-bit display data Read 8-bit command Read 9-bit parameters or status* Write 8-bit command Write 9-bit display data Rev 1.4 SSD2119 ...
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... D[17: D[17: Jun 2009 /RD /CS SSD2119 DC /WR D[17:0] DC /CS Operation 0 0 Read 8-bit command 1 0 Read 8-bit parameters or status Write 8-bit command 1 0 Write 16-bit display data 0 0 Read 8-bit command 1 0 Read 8-bit parameters or status* ...
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... GG2 GG1 GG0 BB4 BB3 BB2 BB1 BB0 Jun 2009 P 80/95 Rev 1.4 SSD2119 ...
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... SCL SDI D 4-wire SPI write display data SDC SCS 1 2 SCL SDI Rev 1.4 P 81/95 SSD2119 D Jun 2009 ...
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... Line Line Line Line Line Line Line Line Line Line Jun 2009 P 82/95 Rev 1.4 SSD2119 ...
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... DISPLAY SETTING SEQUENCE 16 16.1 Display ON Sequence Rev 1.4 P 83/95 SSD2119 Power supply setting Set R07h at 0021h GON = 1 DTE = 0 D[1: Set R00h at 0001h Set R07h at 0023h GON = 1 DTE = 0 D[1: Set R10h at 0000h Exit sleep mode Wait 30ms Set R07h at 0033h GON = 1 DTE = 1 D[1: Entry Mode setting (R11h) ...
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... If OTP is active in the application, the OTP programming voltage should be turned off and cap discharged before VCI/VDDIO are turned off. Solomon Systech Display ON Set R10h at 0001h Enter sleep mode Set R07h at 0000h Halt the operation Wait unit VGH < 5V Remove power from V , then remove V CI Display OFF 500ms DDIO Jun 2009 P 84/95 Rev 1.4 SSD2119 ...
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... Halt Sequence Rev 1.4 P 85/95 SSD2119 Display ON Pull-low RESB Halt Pull-up RESB Set R07h at 0000h Send Initial code to SSD2119 Display ON Jun 2009 Solomon Systech ...
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... Solomon Systech Display ON Set R10h at 0001h Set R07h at 0000h wait for 1.5 frame e.g. for 60Hz – 25ms Sleeping Release from Sleep Set R10h at 0000h Set R07h at 0033h Set R07h at 0000h wait for 10 frames e.g. for 60Hz – 166.7ms Display ON Jun 2009 P 86/95 Rev 1.4 SSD2119 ...
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... Deep Sleep Mode Display Sequence Rev 1.4 P 87/95 SSD2119 Display ON Set R10h at 0001h Set R12h at 2999h Set R07h at 0000h Sleeping Set R12h at 0999h Release from Sleep Set R10h at 0000h Set R07h at 0000h Set R07h at 0033h Display ON Jun 2009 Ivci = 66uA Ivci = 2uA wait for 1.5 frame e.g. for 60Hz – ...
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... V V CDUM0 COMH COML GL Regulator Circuit & VCOM Generator Circuit Grayscale VLCD63 Generator Regulator Circuit Gate Driver Generator System Interface / Control Logic V LCD63 Source driver Gamma / Switches Network Voltage Data Latches GDDRAM OSC / Address Timing Counter Jun 2009 P 88/95 Rev 1.4 VCOM SSD2119 ...
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... SSD2119 OUTPUT VOLTAGE RELATIONSHIP VCOMH (max 5V) VCI (2.5~3.6V) VSS Note: VGH-VGL<30V p-p Rev 1.4 P 89/95 SSD2119 VLCD63 (max 5.5V) VCOM amplitude (max 5.5V) VCOML Jun 2009 VGH (9~18V) VGL (-6~ -15V) Solomon Systech ...
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... Solomon Systech Figure 19-1: Booster Capacitors All capacitors 0.1 ~ 0.22uF (0.22uF for better stability) Mandatory requirement on external components for SSD2119 is 10 capacitors. VSS VCIX2, VCIM, VGH, VGL, VCI, VCORE, VCOMH, VCOML C1P/C1N, C2P/C2N, C3P/C3N, CYP/CYN, CXP/CXN Remark: Capacitor for VCIX2 = 2.2uF VCI should be separated with VCIP at ITO layout to provide noise free path ...
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... G1-G240 Rev 1.4 P 91/95 SSD2119 Figure 19-3: Panel Connection Example 32RGB x 240 TFT Panel (Cs on Common) 960 S1-S960 SSD2119 Jun 2009 VCOM Solomon Systech ...
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... D5 100 D4 100 D3 100 D2 100 D1 100 D0 10 VSS 100 DOTCLK 100 HSYNC 100 VSYNC 100 DEN 10 VSS 100 PS0 10 VDDIO 100 PSI 10 VSS 100 PS2 10 VDDIO 100 PS3 10 VSS Rev 1.4 SSD2119 ...
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... PACKAGE INFORMATION 20.1 Chip Tray Information SSD2119Z7 Rev 1.4 P 93/95 SSD2119 Jun 2009 Solomon Systech ...
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... OTP DETAIL Fresh die 1) Example 1 - VCMR[5: default A fresh SSD2119 will have the OTP register default value of OTPR[5:0]=0x00 and default value of VCMR[5:0]=0x2B, which corresponds to base values [110110] from the 6 least significant bits. VCOMH = VCMR XOR OTPR 2) Example 2 - VCM[5:0] is adjusted and nOTP=1 nOTP=1 will override the default VCOMH value and is used together with VCM[5:0] to find out the optimal value against flickering ...
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... Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with control Marking Symbol . Hazardous Substances test report is available upon requested. http://www.solomon-systech.com Rev 1.4 P 95/95 SSD2119 Jun 2009 Solomon Systech ...