MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet - Page 64

• Manufacturer Part Number: MCMC68HC05L16
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Oscillators/Clock Distributions
7.5.4 COP
The computer operating properly (COP) watchdog timer is controlled by the COPE and COPC bits in the
TBCR2 register.
The COP uses the same clock as TBI that is selected by the TBR1 and TBR0 bits. The TBI is divided by
four and overflow of this divider generates COP timeout reset if the COP enable (COPE) bit is set. The
COP timeout reset has the same vector address as POR and external RESET. To prevent the COP
timeout, the COP divider is cleared by writing a logic1 to the COP clear (COPC) bit.
When the timebase divider is driven by the OSC clock, clock for the divider is suspended during stop
mode or when FOSCE is a logic 0. This may cause COP period stretching or no COP timeout reset when
processing errors occur. To avoid these problems, it is recommended that the XOSC clock be used for
the COP functions.
When the timebase (COP) divider is driven by the XOSC clock, the divider does not stop counting and
the COPC bit must be triggered to prevent the COP timeout.
64
TBR
TBR1
1
0
0
1
1
TBCR2
0
0
1
1
TBCR2
TBR
0
0
1
0
1
TBR0
0
1
0
1
TBCLK ÷ 16,384
TBCLK ÷ 4096
TBCLK ÷ 8192
TBCLK ÷ 128
Divide Ratio
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Table 7-3. Timebase Interrupt Frequency
1573
OSC = 4.0 MHz
12.3
Min
393
786
Table 7-4. COP Timeout Period
1048
2097
Max
16.4
524
OSC = 4.0 M
7.63
3.81
1.91
244
OSC = 4.1943 MHz
1500
11.7
Min
375
750
COP Period (ms)
OSC = 4.1943 M
Frequency (Hz)
1000
2000
Max
15.6
500
8.00
4.00
2.00
256
XOSC = 32.768 kHz
1500
11.7
Min
375
750
XOSC = 32.768 k
8.00
4.00
2.00
256
Freescale Semiconductor
1000
2000
Max
15.6
500