ADN2807 Analog Devices, Inc., ADN2807 Datasheet
ADN2807
Related parts for ADN2807
ADN2807 Summary of contents
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... The receiver front end signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2807 is available in a compact 7 mm × 48-lead chip-scale package (LFCSP). FUNCTIONAL BLOCK DIAGRAM VEE ...
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... ADN2807 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Definition of Terms .......................................................................... 8 Maximum, Minimum, and Typical Specifications ................... 8 Input Sensitivity and Input Overdrive....................................... 8 Single-Ended vs. Differential ...................................................... 8 LOS Response Time ..................................................................... 9 Jitter Specifications....................................................................... 9 Theory of Operation ...................................................................... 10 Functional Description .................................................................. 12 Multirate Clock and Data Recovery......................................... 12 REVISION HISTORY 5/04— ...
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... THRESH kΩ THRESH kΩ THRESH OC-3, PRBS kΩ THRESH kΩ THRESH kΩ THRESH From f error > 1000 ppm VCO Rev Page ADN2807 Min Typ Max Unit 0 1.2 V 2.4 V 0.4 V – p p-p 500 µV 244 µV rms ...
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... ADN2807 Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Jitter Tolerance CML OUTPUTS (CLKOUTP/N, DATAOUTP/N) Single-Ended Output Swing Differential Output Swing Output High Voltage Output Low Voltage Rise Time Fall Time Setup Time Hold Time REFCLK DC INPUT CHARACTERISTICS Input Voltage Range ...
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... Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. THERMAL CHARACTERISTICS Rating Thermal Resistance 5.5 V 48-Lead LFCSP, 4-layer board with exposed paddle soldered VEE – 0 VCC VCC + 0.4 V 165°C θ = 25°C/W JA –65°C to +150°C 300°C Rev Page ADN2807 ...
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... SDOUT DO 48 LOOPEN DI 1 Type Power Analog Input Analog Output Digital Input Digital Output THRADJ 1 PIN 1 VCC 2 INDICATOR VEE 3 VREF 4 PIN 5 ADN2807 NIN 6 SLICEP 7 TOPVIEW SLICEN 8 VEE 9 LOL 10 XO1 11 XO2 12 Figure 2. Pin Configuration Description LOS Threshold Setting Resistor. Analog Supply. Ground. ...
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... RESISTANCE (kΩ) Figure 4. LOS Comparator Trip Point Programming DIFF Rev Page ADN2807 90 100 HYSTERESIS (dB) Figure 6. LOS Hysteresis OC-12, −40°C, 3 –1 PRBS Input Pattern kΩ ...
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... SINGLE-ENDED VS. DIFFERENTIAL AC coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc-biased to a common- mode potential of ~0.6 V. Driving the ADN2807 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 9 shows a binary signal with average value equal to the common-mode potential and instantaneous values both above and below the average value ...
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... The LOS response time is the delay between the removal of the input signal and indication of loss of signal (LOS) at SDOUT. The ADN2807’s response time is 300 ns typ when the inputs are dc-coupled. In practice, the time constant of ac coupling at the quantizer input determines the LOS response time. ...
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... ADN2807 THEORY OF OPERATION The ADN2807 is a delay-locked and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of the input jitter ...
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... MHz for OC-12 data rates and 600 kHz for OC-3 data rates. JITTER GAIN (dB) n psh Figure 14. Jitter Response vs. Conventional PLL Rev Page ADN2807 JITTER PEAKING IN ORDINARY PLL ADN2807 Z(s) X(s) f (kHz) d psh o c ...
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... ADN2807 FUNCTIONAL DESCRIPTION MULTIRATE CLOCK AND DATA RECOVERY The ADN2807 recovers clock and data from serial bit streams at OC-3, OC-12 data rates as well as the 15/14 FEC rates. The output of the 2.5 GHz VCO is divided down in order to support the lower data rates. The data rate is selected by the SEL[2..0] inputs (Table 5) ...
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... OSCILLATOR XO2 REFSEL Figure 17. Crystal Oscillator Configuration The ADN2807 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/ LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/ LVDS levels via the REFCLKN/P inputs, independent of data rate. The input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (e ...
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... CML outputs. Bypass and loop-back modes are mutually exclusive; only one of these modes can be used at any given time. The ADN2807 is put into an indeterminate state if both BYPASS and LOOPEN pins are set to Logic 1 at the same time. Rev Page ...
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... PCB. Use of 0.1 µF and 1 nF ceramic chip capacitors should be placed between IC power supply VCC and GND as close as possible to the ADN2807’s VCC pins. Again, if connections to the supply and ground are made through vias, the use of multiple vias in parallel will help to reduce series inductance, especially on Pins 35 and 36, which supply power to the high speed CLKOUTP/N and DATAOUTP/N output buffers ...
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... VEE 34 VEE 33 SEL0 µ SEL1 µC 30 VEE 29 VCC 28 0.1µF VEE 1nF 27 VCC 26 CF2 25 4.7µF (SEE TABLE 8 FOR SPECS) VCC 0.1µF VCC ADN2807 C 50Ω IN PIN TIA C 50Ω IN NIN 50Ω VREF 0.1µ F Figure 22. AC-Coupled Input Configuration VCC VCC 50Ω ...
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... THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2807. THE QUANTIZER WILL BE ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... ADN2807 VCC ADN2807 50Ω PIN TIA 50Ω NIN 50Ω VREF 0.1µ F Figure 24. ADN2807 with DC-Coupled Inputs INPUT (V) V p-p = PIN – NIN = 2 × 10mV AT SENSITIVITY SE PIN NIN Figure 25. Minimum Allowed DC-Coupled Input Levels INPUT (V) 50Ω 5mV MIN 0.4V MIN CM (DC-COUPLED) Rev Page p-p = PIN – ...
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... REF COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 27. 48-Lead Lead Frame Chip Scale Package [LFCSP × Body (CP-48) Dimensions shown in millimeters Package Description 48-Lead LFCSP 48-Lead LFCSP Rev Page 0.30 0.23 0.60 MAX 0.18 PIN 1 INDICATOR 48 1 5.25 BOTTOM 5.10 SQ VIEW 4. 0.25 MIN 5.50 REF Package Option CP-48 CP-48 ADN2807 ...
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... ADN2807 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03877–0–5/04(A) Rev Page ...