ADN2813 Analog Devices, Inc., ADN2813 Datasheet
ADN2813
Related parts for ADN2813
ADN2813 Summary of contents
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... The receiver front-end, loss-of-signal (LOS) detector circuit indicates when the input signal level has fallen below a user- adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2813 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM REFCLKP/N ...
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... ADN2813 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Jitter Specifications....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Timing Characteristics..................................................................... 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. Interface Timing and Internal Register Description........... 10 Terminology ...
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... kΩ THRESH 2 DC-coupled 2 DC-coupled With respect to nominal With respect to nominal 10 Mb/s OC-12 GbE GbE OC-12 OC-3 OC-1 10 Mb/s See Table 13 In addition to REFCLK accuracy Data rate ≤ 20 Mb/s Data rate > 20 Mb/s Rev Page ADN2813 23 − 1, Min Typ Max Unit 1.8 2.8 V 2.0 V 2.3 2.5 2 3.3 mV p-p 500 μV 290 μV rms ...
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... Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Jitter Tolerance 1 Jitter tolerance of the ADN2813 at these jitter frequencies is better than what the test equipment is able to measure. Conditions Locked to 1.25 Gb/s , VEE = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2 F Conditions ...
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... 2 2 0.4 V − −2 Rev Page ADN2813 Typ Max Unit 1475 mV mV 320 400 mV 300 400 1200 1275 mV 100 Ω 115 220 ps 115 220 ps 400 440 ps 400 440 ps V 0.3 VCC V +10 ...
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... ADN2813 ABSOLUTE MAXIMUM RATINGS VCC = MIN MAX MIN MAX 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device ...
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... TIMING CHARACTERISTICS CLKOUTP DATAOUTP Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R V LOAD DIFF 100Ω 100Ω 5mA SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev Page ADN2813 ...
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... Exposed Pad Pad P 1 Type power analog input analog output digital input digital output. TEST1 1 PIN 1 INDICATOR VCC 2 VREF 3 ADN2813* NIN 4 PIN 5 TOP VIEW (Not to Scale) SLICEP 6 SLICEN 7 VEE 8 * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. ...
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... TYPICAL PERFORMANCE CHARACTERISTICS 100 1k R (Ω) TH Figure 6. LOS Comparator Trip Point Programming 10k 100k Rev Page ADN2813 ...
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... ADN2813 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 A5 SCK S SLADDR[4... SDA t LOW SCK t S SLAVE ADDRESS [6... MSB = 1 SET BY PIN 19 Figure 7 ...
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... System Reset D5 Write a 1 followed reset ADN2813 Config. LOS SQUELCH Mode Set Active high LOS 0 = SQUELCH CLK and DATA 1 = Active low LOS 1 = SQUELCH CLK or DATA Rev Page LSB ...
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... LOS output, Pin 22. When the inputs are dc-coupled, the LOS assert time of the ADN2813 is 500 ns typical and the deassert time is 400 ns typical. In practice, the time constant produced by the ac coupling at the quantizer input and the 50 Ω on-chip input termination determines the LOS response time ...
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... The following sections briefly summarize the specifications of jitter generation, transfer, and tolerance in accordance with the Telcordia document (GR-253-CORE, Issue 3, September 2000) for the optical interface at the equipment level and the ADN2813 performance with respect to those specifications. Jitter Generation The jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input ...
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... ADN2813 THEORY OF OPERATION The ADN2813 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter ...
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... The jitter accommodation is roughly 0 this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 1.5 MHz at 1.25 Gb/s. Rev Page ADN2813 ...
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... The lock detector on the ADN2813 has three modes of operation: normal mode, REFCLK mode, and static LOL mode. Normal Mode In normal mode, the ADN2813 is a continuous rate CDR that locks onto any data rate from 10 Mb/s to 1.25 Gb/s without the use of a reference clock as an acquisition aid. In this mode, the ...
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... This hysteresis is shown in Figure 20. Static LOL Mode The ADN2813 implements a static LOL feature, which indicates if a loss-of-lock condition has ever occurred and remains asserted, even if the ADN2813 regains lock, until the static LOL 2 bit is manually reset. The I C register bit, MISC[4], is the static LOL bit ...
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... If an invalid subaddress is issued by the user, the ADN2813 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while reading back in ...
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... MHz. CTRLA[5:2] is set to [0101], that is, 5, because 622.08 Mb/s/19.44 MHz = 2 In this mode, if the ADN2813 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2813 is operating in lock-to-reference mode, if ...
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... A fine data rate readback is then executed as follows: 1. Write CTRLA[1]. This enables the fine data rate measurement capability of the ADN2813. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. ...
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... Use μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2813 VCC pins. VCC + 22μF 0.1μ ...
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... UI p-p typical the rise time, which is equal to 0.22/BW, where BW ~ 0.7 r (bit rate). Note that this expression for t The output rise time for the ADN2813 is ~100 ps regardless of data rate. Rev Page –t/τ ); therefore, τ = 12t (−nT/RC) = 0.5t (1 − e )/0 ...
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... EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2813. THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... ADN2813 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code F Code MID 0 5.3745e+ 5.3741e+ 5.4793e+ 5.5912e+ 5.7111e+ 5.8391e+ 5.9760e+ 6.1215e+ 6.2780e+ 6.4565e+ ...
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... Rev Page ADN2813 Code F MID 240 9.8129e+08 241 9.8124e+08 242 1.0012e+09 243 1.0225e+09 244 1.0453e+09 245 1.0697e+09 246 1.0959e+09 247 1.1239e+09 248 1 ...
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... PIN 1 INDICATOR VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADN2813ACPZ −40°C to 85°C 1 ADN2813ACPZ-500RL7 −40°C to 85°C 1 ADN2813ACPZ-RL7 −40°C to 85°C EVAL-ADN2813EB Pb-free part. 5.00 0.60 MAX 0.50 BSC TOP 4.75 BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.23 ...
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... NOTES Rev Page ADN2813 ...
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... ADN2813 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...