ADN2813 Analog Devices, Inc., ADN2813 Datasheet - Page 20

• Manufacturer Part Number: ADN2813
• Description: Continuous Rate 10 Mb/s To 1.25 Gb/s Clock And Data Recovery Ic With Integrated Limiting Amp
• Manufacturer: Analog Devices, Inc.

ADN2813
The reference clock can range from 10 MHz and 160 MHz.
The ADN2813 expects a reference clock between 10 MHz
and 20 MHz by default. If it is between 20 MHz and 40 MHz,
40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs
to configure the ADN2813 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner in
which the part locks onto data. In this mode, the reference clock
is used only to determine the frequency of the data. For this
reason, the user does not need to know the data rate to use the
reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
1. Write a 1 to CTRLA[1]. This enables the fine data rate
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
3. Read back MISC[2]. If it is 0, the measurement is not
4. Read back the data rate from FREQ2[6:0], FREQ1[7:0],
The data rate can be determined by
where:
FREQ[22:0] is the reading from FREQ2[6:0] MSByte,
FREQ1[7:0], and FREQ0[7:0] LSByte (see Table 12).
f
f
SEL_RATE is the setting from CTRLA[7:6].
Table 12.
D22
DATARATE
REFCLK
measurement capability of the ADN2813. This bit is level
sensitive and does not need to be reset to perform
subsequent frequency measurements.
This initiates a new data rate measurement.
complete. If it is 1, the measurement is complete and the
data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
and FREQ0[7:0].
f
DATARATE
is the REFCLK frequency (MHz).
is the data rate (Mb/s).
D21...D17
=
(
FREQ
FREQ2[6:0]
[
22
..
0
]
×
f
REFCLK
D16
)
/
2
(
14
+
SEL
_
RATE
D15
)
Rev. 0 | Page 20 of 28
D14...D9
FREQ1[7:0]
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting is [01], because
the reference frequency falls into the 20 MHz to 40 MHz range.
Assume for this example that the input data rate is 1.25 Gb/s
(GbE). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x138800, which is equal to
1.28 × 10
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
Additional Features Available via the I
Coarse Data Rate Readback
The data rate can be read back over the I
approximately ±10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The eight MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
Table 13 provides coarse data rate readback to within ±10%.
LOS Configuration
The LOS detector output, Pin 22, can be configured to be either
active high or active low. If CTRLC[2] is set to Logic 0 (default),
the LOS pin is active high when a loss-of-signal condition is
detected. Writing a 1 to CTRLC[2] configures the LOS pin to be
active low when a loss-of-signal condition is detected.
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
frequency acquisition while keeping the ADN2813 in the
operating mode that it was previously programmed to in
Registers CTRL[A], CTRL[B], and CTRL[C].
128e6 × 32e6/2
6
. Plugging this value into the equation yields
D8
2
C Register Bit CTRLB[5]. This initiates a new
(14 + 1)
D7
= 1.25 Gb/s
D6...D1
FREQ0[7:0]
2
C interface to
2
C Interface
D0