ADN2530 Analog Devices, Inc., ADN2530 Datasheet
ADN2530
Related parts for ADN2530
ADN2530 Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. 11.3 Gbps, Active Back-Termination, GENERAL DESCRIPTION The ADN2530 laser diode driver is designed for direct modula- tion of packaged VCSELs with a differential resistance ranging from 35 Ω to 140 Ω. The active back-termination technique provides excellent matching with the output transmission lines while reducing the power dissipation in the output stage ...
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... ADN2530 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Package Thermal Specifications ................................................. 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Input Stage................................................................................... 10 Bias Current ................................................................................ 10 REVISION HISTORY 8/06—Rev Rev. A Changes to Figure 1.......................................................................... 1 Changes to Table 3 ...
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... V 0.8 V −20 +20 μA 0 200 μA Rev Page ADN2530 Test Conditions/Comments ALS = high IBIAS = 25 mA IBIAS = Ω to 100 Ω differential LOAD R = 140 Ω differential LOAD ALS = high CPA disabled CPA 35% to 65% CPA disabled CPA 35% to 65% CPA disabled CPA 35% to 65% 10 ...
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... The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate. 7 Only includes current in the ADN2530 VCC pins. 8 Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation. PACKAGE THERMAL SPECIFICATIONS Table 2. Parameter Min θ ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev Page ADN2530 ...
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... DATAN 16 VCC Exposed Pad Pad MSET BSET 1 12 PIN 1 INDICATOR IBMON CPA 2 11 ADN2530 ALS IBIAS 3 10 TOP VIEW GND GND 4 9 (Not to Scale) NOTES: THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO THE VCC OR GND PLANE. Figure 4. Pin Configuration ...
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... Figure 8. Deterministic Jitter vs. IMOD 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 JITTER BELOW EQUIPMENT 0.2 MEASUREMENT CAPABILITY 0 DIFFERENTIAL MODULATION CURRENT (mA) Figure 9. Random Jitter vs. IMOD 0 –5 –10 –15 –20 –25 –30 –35 – FREQUENCY (GHz) Figure 10. Differential |S22| ADN2530 ...
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... ADN2530 –40 – TEMPERATURE (°C) Figure 11. Rise Time vs. Temperature (Worse-Case Conditions, CPA Disabled –40 – TEMPERATURE (°C) Figure 12. Fall Time vs. Temperature (Worst-Case Conditions, CPA Disabled) 1.0 0.8 0.6 0.4 0.2 0 –40 – TEMPERATURE (°C) Figure 13. Random Jitter vs. Temperature (Worst-Case Conditions, CPA Disabled [Worst-Case IMOD = 2 ...
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... Figure 19. Worst-Case Fall Time Distribution 20 25 (IMOD = 10 mA, PRBS31 Pattern at 10.3125 Gbps Figure 21. Filtered 10G Ethernet Optical Eye Using AOC HFE6192-562 VCSEL (PRBS31 Pattern at 10.3125 Gbps Optical Attenuator Rev Page ADN2530 1 LEVEL 1 LEVEL CROSSING 0 LEVEL 0 LEVEL Figure 20. Electrical Eye Diagram ...
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... Generally, this is achieved using 100 nF capacitors. 50Ω 50Ω DATA SIGNAL SOURCE Figure 23. AC Coupling the Data Source to the ADN2530 Data Inputs BIAS CURRENT The bias current is generated internally using a voltage-to-current converter consisting of an internal operational amplifier and a transistor, as shown in Figure 24. ...
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... IBIAS and IMOD Disabled Enabled Enabled VCC VCC 100Ω ALS 35kΩ 2kΩ Figure 29. Equivalent Circuit of the ALS Pin VCC 100Ω FROM CPA STAGE 800Ω 200Ω ADN2530 GND Figure 30. Generation of Modulation Current on the ADN2530 ADN2530 IMODP IMOD IMODN ...
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... MSET pin able to drive 23 mA modulation currents through the differential load, the output stage of the ADN2530 (IMODP and IMODN pins) must be ac-coupled to the load. The voltages at these pins have a dc component equal to VCC and an ac component with single-ended peak-to-peak amplitude of IMOD × ...
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... TOSAs have differential resistance not equal to 100 Ω. In this case, with 100 Ω differential transmission lines connecting the ADN2530 to the load, the load end of the transmission lines are misterminated. This mistermination leads to signal reflections back to the driver. The excellent back-termination in the ADN2530 absorbs these reflections, preventing their reflection back to the load ...
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... TOP T is the temperature at package exposed paddle in degrees PAD Celsius the IC junction temperature in degrees Celsius the ADN2530 power dissipation in watts. θ is the thermal resistance from IC junction to package top. J-TOP θ is the thermal resistance from IC junction to package J-PAD exposed pad. ...
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... APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT Figure 39 shows the typical application circuit for the ADN2530. The dc voltages applied to the BSET and MSET pins control the bias and modulation currents. The bias current can be monitored as a voltage drop across the 750 Ω resistor connected between the IBMON pin and GND ...
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... BSET and MSET Pin Voltage Calculation To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2530 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1 ...
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... IBMON output current of ±5.25% of the nominal IBIAS value over all operating conditions. The IBMON output current accuracy numbers can be combined with the accuracy numbers for the 750 Ω IBMON resistor (R sources to calculate an overall accuracy for the IBMON voltage. Rev Page ADN2530 100 = × ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 0.90 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range ADN2530YCPZ-WP 1 −40°C to +100°C 1 ADN2530YCPZ-R2 −40°C to +100°C 1 ADN2530YCPZ-REEL7 −40°C to +100° Pb-free part. 3.00 0.60 MAX BSC SQ 0. 2.75 TOP BSC SQ VIEW 9 (BOTTOM VIEW) 0.50 8 BSC 1.50 REF ...
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... NOTES Rev Page ADN2530 ...
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... ADN2530 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05457–0–8/06(A) Rev Page ...