ICM7170 Intersil Corporation, ICM7170 Datasheet
ICM7170
Available stocks
Related parts for ICM7170
ICM7170 Summary of contents
Page 1
... Copyright Microprocessor-Compatible, Real-Time Clock Description The ICM7170 real time clock is a microprocessor bus compatible peripheral, fabricated using Intersil’s silicon gate CMOS LSl process. An 8-bit bidirectional bus is used for the data I/O circuitry. The clock is set or read by accessing the 8 ...
Page 2
... OUT INTERRUPTS LOW COMPARE POWER PERIODIC OSC TIME COUNTERS 0.01 SEC MIN HOUR DAY DATE MON YEAR 8 8-BIT BUS 8 0.01 SEC MIN HOUR DAY DATE MON YEAR COMPARE RAM 12-6 ICM7170 (SOIC) TOP VIEW OSC OUT OSC IN ...
Page 3
... Due to the SCR structure inherent in the CMOS process, connecting any terminal at voltages greater than V destructive device latchup. For this reason recommended that no inputs from external sources not operating on the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7170 be turned on first. 3. ...
Page 4
... ADDRESS to ALE Set Up Time ADDRESS Hold Time After ALE ICM7170 - +5V 10 BACKUP specifications include all input and output leakages (ICM7170 and ICM7170A) (Contin- DD TEST CONDITIONS INT SOURCE O DD Connected - ...
Page 5
... A0 - A4, CS xxxxxxxxxx FIGURE 2. WRITE CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = V ADDRESS VALID, CS LOW D7, CS ALE RD FIGURE 3. READ CYCLE TIMING FOR MULTIPLEXED BUS ( ICM7170 ADDRESS VALID, CS LOW t CYC t RD OUTPUT DATA VALID t ACC ADDRESS VALID, CS LOW t t CYC ...
Page 6
... DD RD COMMAND REGISTER ADDRESS (10001b, 11h) WRITE-ONLY n/a n/a Normal/Test Mode TABLE 2. COMMAND REGISTER BIT ASSIGNMENTS INTERRUPT D5 TEST BIT D4 ENABLE 0 Normal Mode 0 Interrupt disabled 1 Test Mode 1 Interrupt enable ICM7170 SOIC PIN NUMBER ...
Page 7
... TABLE 4. INTERRUPT AND STATUS REGISTERS FORMAT INTERRUPT MASK REGISTER ADDRESS (10000b, 10h) WRITE-ONLY D7 D6 NOT USED DAY INTERRUPT STATUS REGISTER ADDRESS (10000b, 10h) READ-ONLY D7 D6 GLOBAL INTERRUPT DAY Periodic and Alarm Flags ICM7170 TABLE 3. ADDRESS CODES AND FUNCTIONS FUNCTION D7 D6 Counter-1/100 seconds - Counter-hours - - 12 Hour Mode - † ...
Page 8
... Bit D7 is the global interrupt bit, and when set to a “1”, indicates that the ICM7170 did indeed generate a hardware interrupt. This is useful when other interrupting devices in addition to the ICM7170 are attached to the system microprocessor, and all devices must be polled to determine which one generated the interrupt ...
Page 9
... FIGURE 5. INTERRUPT OUTPUT CIRCUIT battery backup, device operation is limited to timekeeping and interrupt generation only, thus achieving micro- power current drain external battery-backup switch-over circuit is being used with the ICM7170 standby battery operation is not required, the resistor. Time Synchronization ...
Page 10
... PIN 13 DIGITAL GROUND FIGURE 6. SIMPLIFIED ICM7170 BATTERY BACKUP CIRCUIT logical “0” shown in Figures 2 and 3. The ICM7170 will also work satisfactorily with CS grounded. In this mode, access to the ICM7170 is controlled by RD and WR only. With the ALE (Address Latch Enable) input, the ICM7170 ...
Page 11
... U3, which is functioning as an I/O block address decoder. DS1 selects the interrupt priority used to isolate the ICM7170 from the PC databus for test purposes only required on heavily-loaded TTL databuses - the ICM7170 can drive most TTL and CMOS databuses directly ...
Page 12
... U2 ICM7170 SR2 + OPTIONAL DIODE AND RESISTOR SEE NOTE 8 FIGURE 9. IBM PC INTERFACE FOR ICM7170Y 12- 74LS139 ...
Page 13
... I/O and provide enough BACKUP SS overdrive for the comparator. 5. ICM7170A PART - The ICM7170A part is binned at final test for a 32.768kHz maximum current All other specifications remain the same. 6. INTERRUPTS - The Interrupt Status Register (address 10H) always indicates which of the real time counters have been in- cremented since the last time the register was read ...