ICM7170 Intersil Corporation, ICM7170 Datasheet - Page 13

• Manufacturer Part Number: ICM7170
• Description: Microprocessor-compatible, Real-time Clock
• Manufacturer: Intersil Corporation

General Notes
1. TIME ACCESS - To update the present time registers (Hex 00 -
2. REGULATED OSClLLATOR - The oscillator’s power supply is
3. INTERNAL BATTERY BACKUP - When the ICM7170 is using its
4. EXTERNAL BATTERY BACKUP - The ICM7170 may be placed
5. ICM7170A PART - The ICM7170A part is binned at final test for
6. INTERRUPTS - The Interrupt Status Register (address 10H)
07) the
registers (Hours, Minutes, Seconds, Month, Date, Day, and Year)
data are latched only if the 1/100 second counter register is read.
The 1/100 seconds data itself is not latched. The real time data
will be held in the latches until the
See the data sheet section on LATCHED DATA. None of the
RAM data is latched since it is static by nature.
voltage regulated with respect to V
regulator’s amplitude is
4MHz mode the regulator’s amplitude is
( 2.6V). As a result, signal conditioning is necessary to drive the
oscillator with an external signal. In addition, it is also necessary
to buffer the oscillator’s signal to drive other external clocks be-
cause of its reduced amplitude and offset voltage.
own internal battery backup circuitry, no other circuitry interfaced
to the ICM7170 should be active during standby operation.
When V
equal V
time, the V
using a Lithium battery.
on the same power supply as battery-backed up RAM by keep-
ing the ICM7170 in its operational state and having an external
circuit switch between system and backup power for the
ICM7170 and the RAM. In this case V
up to V
“on” in this configuration, its current consumption will typically be
less than a microamp greater than that of standby operation at
the same supply voltage (See Note 9). Proper consideration
must be given to disabling the ICM7170s and the RAMs I/O be-
fore system power is removed. This is important because many
microprocessors can generate spurious write signals when their
supply falls below their specified operating voltage limits. NAND-
ing CS (or WR) with a POWERGOOD signal will create a CS (or
WR) that is only valid when system power is within specifica-
tions. The POWERGOOD signal should be generated by an ac-
curate supply monitor such as the ICL7665 under/over voltage
detector. An alternate method of disabling the ICM7170’s I/O is
to pull V
UP
I/O. Do not allow V
oscillation of the battery backup comparator (See Figure 6).
V
overdrive for the comparator.
a 32.768kHz maximum current of 5 A. All other specifications
remain the same.
always indicates which of the real time counters have been in-
cremented since the last time the register was read. NOTE: This
is independent of whether or not any mask bits are set.
The status register is always reset immediately after it is read. If
an interrupt from the ICM7170 has occurred since the last time
the status register was read, bit D7 of the register will be set. If
the source was an alarm interrupt, bit D0 will also be set. If the
interrupt transistor has been turned on, reading the Interrupt
Status Register will reset it.
BACKUP
<1.0V). This will cause the ICM7170 to internally disable all
DD
1
SS
BACKUP
DD
/
100
through a 2K resistor. Although the ICM7170 is always
= V
BACKUP
= 0V. All ICM7170 I/O should also equal V
(+5V) is turned off (Standby operation), V
register must be read first. The 7 real time counter
SS
down to under a volt above V
+ 0.5V will disable the I/O and provide enough
BACKUP
pin should be 2.8V to 3.5V below V
V
to equal V
TN
+ V
1
TP
DD
/
100
SS
BACKUP
( 1.8V). In the 1, 2, and
. In the 32kHz mode the
, since this could cause
seconds is read again.
V
SS
TN
should be pulled
(V
+ V
SS
DD
SS
TN
< V
SS
. At this
should
+ V
BACK-
when
ICM7170
TP
12-17
7. RESlSTOR IN SERIES WITH BATTERY - A 2K resistor (R2)
8. V
9. SUPPLY CURRENT - ICM7170 supply current is predominantly
To enable the periodic interrupt, both the Command Register’s
Interrupt Enable bit (D4) and at least one bit in the Interrupt
Mask Register (D1 - D6) must be set to a 1. The periodic inter-
rupt is triggered when the counter corresponding to a mask bit
that has been set is incremented. For example, if you enable the
1 second interrupt when the current value in the 100ths counter
is 57, the first interrupt will occur 0.43 seconds later. All subse-
quent interrupts will be exactly one second apart. The interrupt
service routine should then read the Interrupt Status Register to
reset the interrupt transistor and, if necessary, determine the
cause of the interrupt (periodic, alarm, or non-ICM7170
generated) from the contents of the status register.
To enable the alarm interrupts, both the Command Register’s
Interrupt Enable bit (D4) and the Interrupt Mask Register’s
Alarm bit (D0) must be set to a 1. Each time there is an exact
match between the values in the alarm register and the values
in the real time counters, bits D0 and D7 of the Interrupt Status
Register will be set to a 1 and the N-channel interrupt transistor
will be turned on. As with a periodic interrupt, the service rou-
tine should then read the Interrupt Status Register to reset the
interrupt transistor and, since periodic and alarm interrupts may
be simultaneously enabled, determine the cause of the interrupt
if necessary.
Mask bits: The ICM7170 alarm interrupt compares the data in
the alarm registers with the data in the real time registers, ignor-
ing any registers with the mask bit set. For example, if the alarm
register is set to 11-23-95 (Month-Day-Year), 10:59:00:00
(Hour-Minutes-Seconds-Hundredths), and DAY = XX (XX =
masked off), the alarm will generate a single interrupt at 10:59
on November 23,1995. If the alarm register is set to 11-XX-95,
10:XX:00:00, and DAY = 2 (2 = Tuesday); the alarm will gener-
ate one interrupt every minute from 10:00-10:59 on every
Tuesday in November, 1995.
NOTE: Masking off the 100ths of a second counter has the
same effect as setting it to 00.
must be placed in series with the battery backup pin of the
ICM7170. The UL laboratories have requested the resistor to
limit the charging and discharging current to the battery. The
resistor also serves the purpose of degenerating parasitic SCR
action. This SCR action may occur if an input is applied to the
ICM7170, outside of its supply voltage range, while it is in the
standby mode.
if discharged at too high a rate. These conditions could occur if
the battery was installed backwards or in the case of a gross
component failure. A 1N914-type diode placed in series with the
battery as shown in Figure 9 will prevent this from occurring. A
resistor of 2M
V
shutting off ICM7170 I/O during normal operation.
a function of oscillator frequency and databus activity. The lower
the oscillator frequency, the lower the supply current. When
there is little or no activity on the data, address or control lines,
the current consumption of the ICM7170 in its operational mode
approaches that of the backup mode.
BACKUP
BACKUP
DIODE - Lithium batteries may explode if charged or
terminal from drifting toward the V
or so should parallel the diode to keep the
SS
terminal and