MBM29LV400TC Fujitsu Microelectronics, Inc., MBM29LV400TC Datasheet - Page 26

• Manufacturer Part Number: MBM29LV400TC
• Description: 4m 512k X 8/256k X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

26
MBM29LV400TC
Notes: 1. Performing successive read operations from any address will cause DQ
RY/BY
Ready/Busy
Byte/Word Configuration
Data Protection
Program
Erase
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
Erase-Suspend Program
The MBM29LV400TC/BC provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29LV400TC/BC are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV400TC/BC devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to Figures 13, 14 and 15 for the timing diagram.
The MBM29LV400TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
logic “1” at the DQ
toggle.
Mode
2
bit. However, successive reads from the erase-suspended sector will cause DQ
-70/-90/-12
8
to DQ
DQ
DQ
DQ
/MBM29LV400BC
0
1
14
7
7
7
bits are tri-stated. However, the command bus cycle is always
0
to DQ
Toggle (Note 1)
7
and the DQ
Toggle
Toggle
DQ
1
6
8
to DQ
6
to toggle.
-70/-90/-12
15
bits are ignored. Refer
1 (Note 2)
Toggle
Toggle
DQ
1
CC
2
power-up
15
/A
CC
-1
.
pin
2
to
0