MX26F128J3 ETC-unknow, MX26F128J3 Datasheet - Page 23

• Manufacturer Part Number: MX26F128J3
• Description: Macronix Nbit Tm Memory Family 128m [x8/x16] Single 3v Page Mode Eliteflash Tm Memory
• Manufacturer: ETC-unknow

P/N:PM0960
Set Block Lock-Bit Commands
This device provided the block lock-bits, to lock and
unlock the individual block. To set the block lock-bit, the
two cycle Set Block Lock-Bit command is requested.
This command is invalid while the WSM is running. Writ-
ing the set block lock-bit command of 60H followed by
confirm command and an appropriate block address.
After the command is written, the device automatically
outputs status register data when read. The CPU can
detect the completion of the set lock-bit event by ana-
lyzing the STS pin output or status register bit SR.7.
Also, reliable operations occur only when VCC and VPEN
are valid. With VPEN _VPENLK , lock-bit contents are
protected against alteration.
Clear Block Lock-Bits Command
All set block lock-bits can clear by the Clear Block Lock-
Bits command. This command is invalid while the WSM
is running. To Clear the block lock-bits, two cycle com-
mand is requested . The device automatically outputs
status register data when read. The CPU can detect
completion of the clear block lock-bits event by analyz-
ing the STS pin output or status register bit SR.7. If a
clear block lock-bits operation is aborted due to V PEN
or VCC transiting out of valid range, block lock-bit values
are left in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit contents to
known values.
Protection Register Program Command
The device offer a 128-bit protection register to increase
the security of a system design. The 128-bits protection
register are divided into two 64-bit segments. One is pro-
grammed in the factory with a unique 64-bit number,
which is unchangeable. The other one is left blank for
customer designers to program as desired. Once the
customer segment is programmed, it can be locked to
prevent reprogramming.
Reading the Protection Register
The protection register is read in the identification read
mode. The device is switched to this mode by writing the
Read Identifier command 90H. Once in this mode, read
cycles from addresses retrieve the specified informa-
23
tion. To return to read array mode, write the Read Array
command (FFH).
Programming the Protection Register
The protection register bits are programmed using the
two-cycle Protection Program command. The 64-bit num-
ber is programmed 16 bits at a time for word-wide parts
and eight bits at a time for byte-wide parts. First write
the Protection Program Setup command, C0H. The next
write to the device will latch in address and data and
program the specified location.
Any attempt to address Protection Program commands
outside the defined protection register address space will
result in a status register error. Attempting to program a
locked protection register segment will result in a status
register error.
Locking the Protection Register
The user-programmable segment of the protection regis-
ter is lockable by programming Bit 1 of the PR-LOCK
location to 0. Bit 0 of this location is programmed to 0 at
the MXIC factory to protect the unique device number.
Bit 1 is set using the Protection Program command to
program "FFFD" to the PR-LOCK location. After these
bits have been programmed, no further changes can be
made to the values stored in the protection register. Pro-
tection Program commands to a locked section will re-
sult in a status register error. Protection register lockout
state is not reversible.
VCC TRANSITIONS
Block erase, program, and lock-bit configuration are not
guaranteed if VCC falls outside of the specified operat-
ing ranges.
The CUI latches commands issued by system software
and is not altered by CE transitions, or WSM actions. Its
state is read array mode upon power-up, after exit from
power-down mode, or after VCC transitions below VLKO.
MX26F128J3
REV. 1.1,OCT. 18, 2004