MX26F128J3 ETC-unknow, MX26F128J3 Datasheet - Page 7

• Manufacturer Part Number: MX26F128J3
• Description: Macronix Nbit Tm Memory Family 128m [x8/x16] Single 3v Page Mode Eliteflash Tm Memory
• Manufacturer: ETC-unknow

P/N:PM0960
FUNCTION
The device includes on-chip program/erase control cir-
cuitry. The Write State Machine (WSM) controls block
erase and byte/word/page program operations. Opera-
tional modes are selected by the commands written to
the Command User Interface (CUI). The Status Register
indicates the status of the WSM and when the WSM
successfully completes the desired program or block
erase operation.
READ
The device has three read modes, which accesses to
the memory array, the Device Identifier or the Status
Register independent of the VPEN voltage. The appro-
priate read command are required to be written to the
CUI. Upon initial device powerup or after exit from
powerdown, the device automatically resets to read ar-
ray mode. In the read array mode, low level input to CE0,
CE1, CE2 and OE, high level input to WE and RESET
and address signals to the address inputs (A23-A0) out-
put the data of the addressed location to the data input/
output (Q15~Q0).
When reading information in read array mode, the de-
vice defaults to asynchronous page mode. In this state,
data is internally read and stored in a high-speed page
buffer. A2:0 addresses data in the page buffer. The page
size is 4 words or 8 bytes. Asynchronous word/byte mode
is supported with no additional commands required.
WRITE
Writes to the CUI enables reading of memory array data,
device identifiers and reading and clearing of the Status
Register and when VPEN=VPENH block erasure pro-
gram and lock-bit configuration. The CUI is written when
the device is enable, WE is active and OE is at high
level. Address and data are latched on the earlier rising
edge of WE and CE. Standard micro-processor write tim-
ings are used.
OUTPUT DISABLE
When OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
7
STANDBY
When CE0, CE1 and CE2 disable the device (see table1)
and place it in standby mode. The power consumption of
this device is reduced. Data input/output are in a high-
impedance(High-Z) state. If the memory is deselected
during block erase, program or lock-bit configuration, the
internal control circuits remain active and the device con-
sume normal active power until the operation completes.
POWER-DOWN
When RESET pin is at VIL the device is in the power-
down mode and its power consumption is substantially
low around 25uA. During read modes, the memory is
deselected and the data input/output are in a high-
impedance(High-Z) state. To return from power down
mode requires RESET pin at VIH. After return from
powerdown, the CUI is reset to Read Array , and the
Status Register is set to value 80H.
During block erase program or lock-bit configuration
modes, RESET pin at VIL will abort either operation.
Memory array data of the block being altered become
invalid.
In default mode, STS transitions low and remains low
for a maximum time of tPLPH+tPHRH until the reset
operation is complete. Memory contents being altered
are no longer valid; the data may be partially corrupted
after a program or partially altered after an erase or lock-
bit configuration. Time tPHWL is required after RESET
goes to logic-high (VIH) before another command can
be written.
READ QUERY
The read query operation outputs block status informa-
tion, CFI (Common Flash Interface) ID string, system
interface information, device geometry information and
MXIC extended query information.
MX26F128J3
REV. 1.1,OCT. 18, 2004