MX29LV017A ETC-unknow, MX29LV017A Datasheet

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MX29LV017A

Manufacturer Part Number
MX29LV017A
Description
16m-bit [2mx8] Cmos Single Voltage
Manufacturer
ETC-unknow
Datasheet

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MX29LV017ATC-70
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MXIC
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MX29LV017ATC-70
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FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 2,097,152 x 8
• Single power supply operation
• Fast access time: 70/90ns
• Low power consumption
• Command register architecture
• Auto Erase (chip & sector) and Auto Program
• Erase suspend/Erase Resume
• Status Reply
GENERAL DESCRIPTION
The MX29LV017A is a 16-mega bit Flash memory orga-
nized as 2M bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29LV017A is
packaged in 40-pin TSOP and 48-ball CSP. It is de-
signed to be reprogrammed and erased in system or in
standard EPROM programmers.
The standard MX29LV017A offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV017A has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV017A uses a command register to manage this
functionality. The command register allows for 100%
P/N:PM0901
- 3.0V only operation for read, erase and program
operation
- 30mA maximum active current
- 0.2uA typical standby current
- Byte Programming (9us typical)
- Sector Erase (Sector structure 64K-Byte x32)
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
1
• Ready/Busy pin (RY/BY)
• Sector protection
• CFI (Common Flash Interface) compliant
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 1.4V
• Package type:
• Compatibility with JEDEC standard
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV017A uses a 2.7V~3.6V VCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
16M-BIT [2Mx8] CMOS SINGLE VOLTAGE
- Data polling & Toggle bit for detection of program and
erase operation completion.
- Provides a hardware method of detecting program or
erase operation completion.
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors.
- Flash device parameters stored on the device and
provide the host system to access
- 40-pin TSOP
- 48-ball CSP
- Pinout and software compatible with single-power
supply Flash
MX29LV017A
3V ONLY FLASH MEMORY
PRELIMINARY
REV. 1.0, NOV. 22, 2002

Related parts for MX29LV017A

MX29LV017A Summary of contents

Page 1

... Status Reply GENERAL DESCRIPTION The MX29LV017A is a 16-mega bit Flash memory orga- nized as 2M bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. The MX29LV017A is packaged in 40-pin TSOP and 48-ball CSP ...

Page 2

... CSP (Ball Pitch=0.8mm) Top View, Balls Facing Down A B A14 A13 RESET 3 RY/ A18 P/N:PM0901 MX29LV017A PIN DESCRIPTION SYMBOL PIN NAME A0~A20 Address Input 40 A17 39 GND Q0~Q7 Data Input/Output 38 A20 CE Chip Enable Input 37 A19 36 A10 WE Write Enable Input 35 ...

Page 3

... BLOCK STRUCTURE Table 1: MX29LV017A SECTOR ARCHITECTURE Sector A20 A19 A18 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 ...

Page 4

... BLOCK DIAGRAM CONTROL CE OE INPUT WE LOGIC RESET ADDRESS LATCH A0-A20 AND BUFFER Q0-Q7 P/N:PM0901 MX29LV017A PROGRAM/ERASE HIGH VOLTAGE FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV DATA LATCH PROGRAM DATA LATCH I/O BUFFER 4 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND DATA ...

Page 5

... Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV017A is less than 18 sec- onds. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the ...

Page 6

... Table 1). The rest of address bits, as shown in Table 2, are don't care. Once all necessary bits have been set as required, the programming equip- ment may read the corresponding identifier code on Q7~Q0. TABLE 2. MX29LV017A AUTOMATIC SELECT MODE BUS OPERATION (A9=VID) Description CE OE Read Silicon ID ...

Page 7

... QUERY COMMAND AND COMMON FLASH INTERFACE(CFI) MODE MX29LV017A is capable of operating in the CFI mode. This mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode ...

Page 8

... Address sensitive unlock (0=required, 1= not required) Erase suspend (2= to read and write) Sector protect ( sectors/group) Temporary sector unprotect (1=supported) Sector protect/chip unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode type (0=not supported) Page mode type (0=not supported) P/N:PM0901 MX29LV017A Address Address 8 Data ...

Page 9

... COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them TABLE 4. MX29LV017A COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID ...

Page 10

... TABLE 5. MX29LV017A BUS OPERATION DESCRIPTION CE Read L Write L Reset X Temporary sector unlock X Output Disable L Standby Vcc±0.3V X Sector Protect L Chip Unprotect L Sector Protection Verify L NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4. 2. VID is the high voltage, 11.5V to 12.5V. ...

Page 11

... ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification P/N:PM0901 MX29LV017A table and timing diagrams for write operations. STANDBY MODE When using both pins of CE and RESET, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. ...

Page 12

... However, multiplexing high volt- age onto address lines is not generally desired system design practice. The MX29LV017A contains a Silicon-ID-Read operation to supple traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Fol- lowing the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H ...

Page 13

... Automatic Select during Erase Suspend goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during Erase Suspend). 13 MX29LV017A Code(Hex ...

Page 14

... Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend Com- P/N:PM0901 MX29LV017A mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. However, when the Erase Suspend com- ...

Page 15

... Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to P/N:PM0901 MX29LV017A this, the device outputs the "complement,” or "0".” The system must provide an address within any of the sec- tors selected for erasure to read valid status information on Q7 ...

Page 16

... Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits P/N:PM0901 MX29LV017A are required for sectors and mode information. Refer to Table 7 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 ...

Page 17

... Q7 (Note1 Erase Suspend Read 1 (Erase Suspended Sector) Erase Suspend Read Data (Non-Erase Suspended Sector) Erase Suspend Program MX29LV017A RY/BY (Note2) Toggle 0 N Toggle Toggle 0 1 Toggle 0 ...

Page 18

... In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX29LV017A powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command se- quences. ...

Page 19

... The system must write the reset command to exit the Automatic Select mode. CHIP UNPROTECT The MX29LV017A also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code recommended to protect all sectors before activating chip unprotect mode ...

Page 20

... This is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. P/N:PM0901 MX29LV017A OPERATING RATINGS Commercial (C) Devices +150 C ...

Page 21

... V 0.7xVCC VCC+ 0.3 V 11.5 12.5 V 0.45 V 0.85xVCC VCC-0.4 1.4 2 MX29LV017A CONDITIONS VIN = 0V VIN = 0V VOUT = 0V CONDITIONS VIN = VSS to VCC, VCC= VCC max VCC=VCC max; A9=12.5V VOUT = VSS to VCC, VCC=VCC max CE=VIL, OE=VIH @5MHz @1MHz CE=VIL, OE=VIH CE; RESET=VCC ± 0.3V RESET=VSS ± 0.3V VIH=VCC ± 0.3V;VIL=VSS ± 0.3V VCC=3.3V IOL = 4.0mA, VCC= VCC min ...

Page 22

... Input rise and fall times is equal to or less than 5ns. • Output load: 1 TTL gate + 100pF (Including scope and jig), for 29LV017A-90. 1 TTL gate + 30pF (Including scope and jig) for 29LV017A-70 • Reference levels for measuring timing: 1.5V. P/N:PM0901 MX29LV017A VCC = 2.7V~3.6V 29LV017A-70 29LV017A-90 MIN ...

Page 23

... AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM0901 CL 6.2K ohm CL=100pF Including jig capacitance (MX29LV017-90) CL=30pF Including jig capacitance (MX29LV017-70) TEST POINTS INPUT 23 MX29LV017A 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT OUTPUT REV. 1.0, NOV. 22, 2002 ...

Page 24

... Figure 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE VIL VIH WE VIL VIH OE VIL HIGH Z VOH Outputs VOL VIH RESET VIL P/N:PM0901 MX29LV017A tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 24 tDF HIGH Z REV. 1.0, NOV. 22, 2002 ...

Page 25

... Write pulse width for sector protect (A9, OE Control) tWPP2 Write pulse width for sector unprotect (A9, OE Control) NOTES: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM0901 MX29LV017A VCC = 2.7V~3.6V 29LV017A-70 MIN. MAX ...

Page 26

... WE Hold Time tCP CE Pulse Width tCPH CE Pulse Width High tWHWH1 Programming Operation(note2) tWHWH2 Sector Erase Operation (note2) NOTE: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM0901 MX29LV017A VCC = 2.7V~3.6V 29LV017A-70 MIN. MAX ...

Page 27

... Figure 2. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE VIL tOES CE VIH VIL tCS OE VIH VIL VIH Data VIL P/N:PM0901 MX29LV017A ADD Valid tAH tWP tCWC tCH tDS tDH DIN 27 tWPH REV. 1.0, NOV. 22, 2002 ...

Page 28

... DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) Read Status Data (last two cycle) tAS PA tAH tCH tWP tWPH tDS tDH A0h PD tBUSY 28 MX29LV017A PA PA tWHWH1 Status DOUT tRB REV. 1.0, NOV. 22, 2002 ...

Page 29

... Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM0901 MX29LV017A START Write Data AAH Write Data 55H Write Data A0H Write Program Data/Address Data Poll from system No Verify Data OK ? YES No Last Address ? YES Auto Program Completed 29 REV. 1.0, NOV. 22, 2002 ...

Page 30

... Figure indicates the last two bus cycles of the command sequence. P/N:PM0901 PA for program SA for sector erase XXX for chip erase Data Polling tAS tAH tWHWH1 or 2 tCPH tBUSY tDH PD for program A0 for program 55 for erase 30 for sector erase 10 for chip erase 30 MX29LV017A PA DOUT Q7 REV. 1.0, NOV. 22, 2002 ...

Page 31

... Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) Read Status Data tAS XXXh tAH tCH tWHWH2 tWP tWPH tDS tDH 55h 10h tBUSY 31 MX29LV017A Progress Complete tRB REV. 1.0, NOV. 22, 2002 ...

Page 32

... Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM0901 MX29LV017A START Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 80H Address XXXH Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 10H Address XXXH Data Poll from System ...

Page 33

... Device outputs 0 dur- ing erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) Read Status Data tAS SA tAH tCH tWHWH2 tWPH 55h 30h tBUSY 33 MX29LV017A Progress Complete tRB REV. 1.0, NOV. 22, 2002 ...

Page 34

... Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM0901 MX29LV017A START Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 80H Address XXXH Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 30H Sector Address NO Last Sector ...

Page 35

... Figure 10. ERASE SUSPEND/ERASE RESUME FLOWCHART P/N:PM0901 START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H ERASE RESUME Continue Erase Another NO Erase Suspend ? YES 35 MX29LV017A REV. 1.0, NOV. 22, 2002 ...

Page 36

... Figure 11. IN-SYSTEM SECTOR PROTECT/CHIP UNPROTECT TIMING WAVEFORM (RESET Con- trol) VID VIH RESET SA, A6 A1, A0 Sector Protect or Chip Unprotect Data 60h 1us Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0. P/N:PM0901 MX29LV017A Valid* Valid* Verify 60h 40h Sector Protect =150us Chip Unprotect =15ms 36 Valid* Status REV. 1.0, NOV. 22, 2002 ...

Page 37

... WE CE Data A20-A16 Notes: tVLHT (Voltage transition time)=4us min. tWPP1 (Write pulse width for sector protect)=100ns min. tOESP (OE setup time to WE active)=4us min. P/N:PM0901 tWPP 1 tOESP Sector Address 37 MX29LV017A Verify tVLHT 01H F0H tOE REV. 1.0, NOV. 22, 2002 ...

Page 38

... Figure 13. SECTOR PROTECTION ALGORITHM (A9, OE Control) No PLSCNT=32? Yes Device Failed P/N:PM0901 MX29LV017A START Set Up Sector Addr PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 150us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector Addr=SA, A6=VIL, A1=VIH, A0=VIL No Data=01H? Yes ...

Page 39

... Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET=VID Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM0901 MX29LV017A START PLSCNT=1 RESET=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H Yes Set up sector address Write 60H to sector address with A6=0, A1=1, A0=0 Wait 150us Verify sector protect : ...

Page 40

... Figure 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET=VID Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM0901 MX29LV017A START PLSCNT=1 RESET=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H ? Yes No All sector Protect all sectors protected? Yes Set up first sector address Chip unprotect : ...

Page 41

... WE CE Data A20-A16 Notes: tVLHT (Voltage transition time)=4us min. tWPP2 (Write pulse width for chip unprotect)=100ns min. tOESP (OE setup time to WE active)=4us min. P/N:PM0901 tWPP 2 tOESP 41 MX29LV017A Verify tVLHT 00H F0H tOE Sector Address REV. 1.0, NOV. 22, 2002 ...

Page 42

... Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0901 MX29LV017A START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 15ms Set OE=CE=VIL A9=VID,A1=1,A6=A0=0 Set Up First Sector Addr ...

Page 43

... WRITE OPERATION STATUS Figure 18. DATA POLLING ALGORITHM NOTE : 1.VA=Valid address for programming or erasure. 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM0901 Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes Read Q7~Q0 Add.=VA Yes Q7 = Data ? (2) No FAIL 43 MX29LV017A Pass REV. 1.0, NOV. 22, 2002 ...

Page 44

... Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM0901 Start Read Q7-Q0 Read Q7-Q0 (Note 1) NO Toggle Bit Q6 = Toggle ? YES Q5= 1? YES Read Q7~Q0 Twice (Note 1,2) NO Toggle bit Q6= Toggle? YES Program/Erase Not Complete,Write operation Complete Reset Command 44 MX29LV017A REV. 1.0, NOV. 22, 2002 ...

Page 45

... VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle. P/N:PM0901 VA tDF tOH Complement Complement True Status Data Status Data True 45 MX29LV017A VA High Z Valid Data High Z Valid Data REV. 1.0, NOV. 22, 2002 ...

Page 46

... VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. P/N:PM0901 VA tDF tOH Valid Status Valid Status (second read) (first read) 46 MX29LV017A VA VA Valid Data Valid Data (stops toggling) REV. 1.0, NOV. 22, 2002 ...

Page 47

... Figure 22. RESET TIMING WAVEFORM RY/BY CE, OE RESET Reset Timing NOT during Automatic Algorithms RY/BY CE, OE RESET Reset Timing during Automatic Algorithms P/N:PM0901 Test Setup All Speed Options Unit tRH tRP tReady2 tReady1 tRP 47 MX29LV017A MAX 20 us MAX 500 ns MIN 500 ns MIN 50 ns MIN 0 ns tRB ...

Page 48

... The system can use toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM0901 Program or Erase Command Sequence Enter Erase Suspend Program Erase Suspend Erase Erase Suspend Read Suspend Program 48 MX29LV017A Test Setup All Speed Options Unit Min 500 ns Min Vcc tVIDR Erase ...

Page 49

... Figure 25. TEMPORARY SECTOR UNPROTECT ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : 1. All protected sectors are temporary unprotected. P/N:PM0901 Start RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH VID=11.5V~12.5V 2. All previously protected sectors are protected again. 49 MX29LV017A REV. 1.0, NOV. 22, 2002 ...

Page 50

... VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A20 VIL CE VIH VIL tCE VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q7 P/N:PM0901 tACC tOE tOH DATA OUT C2H 50 MX29LV017A tDF tOH DATA OUT C8H REV. 1.0, NOV. 22, 2002 ...

Page 51

... Maximum values measured at 85°C, 2.7V, 100,000 cycles. LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins VCC Current Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. P/N:PM0901 MX29LV017A LIMITS MIN. TYP.(2) MAX.(3) 0 ...

Page 52

... ORDERING INFORMATION PART NO. ACCESS TIME (ns) MX29LV017ATC-70 70 MX29LV017ATC-90 90 MX29LV017AXBC-70 70 MX29LV017AXBC-90 90 MX29LV017AXEC-70 70 MX29LV017AXEC-90 90 MX29LV017ATI-70 70 MX29LV017ATI-90 90 MX29LV017AXBI-70 70 MX29LV017AXBI-90 90 MX29LV017AXEI-70 70 MX29LV017AXEI-90 90 P/N:PM0901 MX29LV017A OPERATING CURRENT STANDBY CURRENT MAX.(mA) MAX.(uA PACKAGE 15 40 Pin TSOP (Normal Type Pin TSOP ...

Page 53

... PACKAGE INFORMATION P/N:PM0901 MX29LV017A 53 REV. 1.0, NOV. 22, 2002 ...

Page 54

... P/N:PM0901 MX29LV017A 54 REV. 1.0, NOV. 22, 2002 ...

Page 55

... P/N:PM0901 MX29LV017A 55 REV. 1.0, NOV. 22, 2002 ...

Page 56

... REVISION HISTORY Revision No. Description 1 changed "Advanced Information" to "Preliminary" modify Package Information P/N:PM0901 MX29LV017A Page P1 P53~55 56 Date NOV/22/2002 REV. 1.0, NOV. 22, 2002 ...

Page 57

... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. MX29LV017A ...

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