MX29LV017A ETC-unknow, MX29LV017A Datasheet - Page 12

• Manufacturer Part Number: MX29LV017A
• Description: 16m-bit [2mx8] Cmos Single Voltage
• Manufacturer: ETC-unknow

system can thus monitor RY/BY to determine whether
the reset operation is complete. If RESET is asserted
when a program or erase operation is completed within a
time of tREADY (not during Embedded Algorithms). The
system can read data tRH after the RESET pin returns
to VIH.
Refer to the AC Characteristics tables for RESET
parameters and to Figure 22 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high volt-
age onto address lines is not generally desired system
design practice.
The MX29LV017A contains a Silicon-ID-Read operation
to supple traditional PROM programming methodology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H. A read
cycle with A1=VIL, A0=VIH returns the device code of
C8H for MX29LV017A.
The system must write the reset command to exit the
"Silicon-ID Read Command".
P/N:PM0901
12
AUTOMATIC CHIP ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
The device does not require the system to entirely pre-
program prior to executing the Automatic Chip Erase.
Upon executing the Automatic Chip Erase, the device
will automatically program and verify the entire memory
for an all-zero data pattern. When the device is auto-
matically verified to contain an all-zero pattern, a self-
timed chip erase and verify begin. The erase and verify
operations are completed when the data on Q7 is "1" at
which time the device returns to the Read mode. The
system is not required to provide any control or timing
during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 7), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE or CE pulse, whichever happens first in the
command sequence and terminates when either the data
on Q7 is "1" at which time the device returns to the
Read mode or the data on Q6 stops toggling for two
consecutive read cycles at which time the device re-
turns to the Read mode.
MX29LV017A
REV. 1.0, NOV. 22, 2002