CYP15G0401DXB Cypress Semiconductor Corporation., CYP15G0401DXB Datasheet - Page 23

• Manufacturer Part Number: CYP15G0401DXB
• Description: Quad Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02002 Rev. *L
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate Clock/Data
Recovery (CDR) block within each receive channel. The clock
extraction function is performed by embedded phase-locked
loops (PLLs) that track the frequency of the transitions in the
incoming bit streams and align the phase of their internal
bit-rate clocks to the transitions in the selected serial data
streams.
Each CDR accepts a character-rate (bit-rate
half-character-rate (bit-rate
REFCLK input. This REFCLK input is used to
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits of the range control
monitor, the CDR will switch to track REFCLK instead of the
data stream. Once the CDR output (RXCLKx) frequency
returns back close to REFCLK frequency, the CDR input will
be switched back to track the input data stream. In case no
data is present at the input this switching behavior may result
in brief RXCLKx frequency excursions from REFCLK.
However, the validity of the input data stream is indicated by
the LFIx output. The frequency of REFCLK is required to be
within ±1500 ppm
the REFCLK input of the remote transmitter to ensure a lock
to the incoming data stream.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± inputs through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream and frame to the incoming character bound-
aries. If channel bonding is also enabled, a channel alignment
event is also required before the output data may be
considered usable.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the
bit-clock rate. When enabled, the Framer examines the data
stream, looking for one or more Comma or K28.5 characters
at all possible bit positions. The location of this character in the
data stream is used to determine the character boundaries of
all following characters.
Framing Character
The CYP(V)(W)15G0401DXB allows selection of two
combinations of framing characters to support requirements of
different interfaces. The selection of the framing character is
made through the FRAMCHAR input.
Notes:
15. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth
16. When Receive BIST is enabled on a channel, the Low-Latency Framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character,
• ensure that the VCO (within the CDR) is operating at the
• to reduce PLL acquisition time
• and to limit unlocked frequency excursions of the CDR VCO
correct frequency.
when there is no input data present at the selected Serial
Line Receiver.
bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
which would cause the Receiver to update its character boundaries incorrectly.
[12]
of the frequency of the clock that drives
÷
20) reference clock from the
÷
10) or
The specific bit combinations of these framing characters are
listed in Table 13. When the specific bit combination of the
selected framing character is detected by the Framer, the
boundaries of the characters present in the received data
stream are known.
Table 13. Framing Character Selector
Framer
The Framer on each channel operates in one of three different
modes, as selected by the RFMODE input. In addition, the
Framer itself may be enabled or disabled through the RFEN
input. When RFEN = LOW, the framers in all four receive paths
are disabled, and no combination of bits in a received data
stream will alter the character boundaries. When RFEN
= HIGH, the Framer selected by RFMODE is enabled on all
four channels.
When
selected
character clock until it aligns with the received character
boundaries. In this mode, the Framer starts its alignment
process on the first detection of the selected framing
character. To reduce the impact on external circuits that make
use of a recovered clock, the clock period is not stretched by
more than two bit-periods in any one clock cycle. When
operated with a character-rate output clock (RXRATE = LOW),
the output of properly framed characters may be delayed by
up to nine character-clock cycles from the detection of the
selected
half-character-rate output clock (RXRATE = HIGH), the output
of properly framed characters may be delayed by up to
fourteen character-clock cycles from the detection of the
selected framing character.
When RFMODE = MID (open), the Cypress-mode Multi-Byte
Framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to
incorrect framing due to aliased framing characters in the data
stream. In this mode, the Framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock does not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode, the character boundaries are only
adjusted if the selected framing character is detected at least
twice within a span of 50 bits, with both instances on identical
10-bit character boundaries.
FRAMCHAR
MID (Open)
HIGH
LOW
RFMODE = LOW,
[16]
framing
. This Framer operates by stretching the recovered
Character Name
character.
or Comma−
or +K28.5
Comma+
–K28.5
Bits Detected in Framer
the
CYW15G0401DXB
CYP15G0401DXB
Reserved for test
CYV15G0401DXB
When
Low-Latency
operated
00111110XX
or 11000001XX
0011111010 or
Bits Detected
1100000101
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Framer
with
[15]
is
a
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