CYP15G0401DXB Cypress Semiconductor Corporation., CYP15G0401DXB Datasheet - Page 24

• Manufacturer Part Number: CYP15G0401DXB
• Description: Quad Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02002 Rev. *L
When RFMODE = HIGH, the Alternate-mode Multi-Byte
Framer is enabled. Like the Cypress-mode Multi-Byte Framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the Framer does
not adjust the character clock boundary, but instead aligns the
character to the already recovered character clock. In this
mode, the data stream must contain a minimum of four of the
selected framing characters, received as consecutive
characters, on identical 10-bit boundaries, before character
framing is adjusted.
Framing for all channels is enabled when RFEN = HIGH. If
RFEN = LOW, the Framer for each channel is disabled. When
the framers are disabled, no changes are made to the
recovered character boundaries on any channel, regardless of
the presence of framing characters in the data stream.
10B/8B Decoder Block
The Decoder logic block performs three primary functions:
10B/8B Decoder
The framed parallel output of each Deserializer Shifter is
passed to the 10B/8B Decoder where, if the Decoder is
enabled (DECMODE ≠ LOW), it is transformed from a 10-bit
transmission character back to the original Data and Special
Character codes. This block uses the 10B/8B Decoder
patterns in Table 28 and Table 29 of this data sheet. Valid data
characters are indicated by a 000b bit-combination on the
associated RXSTx[2:0] status bits, and Special Character
codes are indicated by a 001b bit-combination on these same
status outputs. Framing characters, invalid patterns, disparity
errors, and synchronization status are presented as alternate
combinations of these status bits.
The 10B/8B Decoder operates in two normal modes, and can
also be bypassed. The operating mode for the Decoder is
controlled by the DECMODE input.
When DECMODE = LOW, the Decoder is bypassed and raw
10-bit characters are passed to the Output Register. In this
mode, channel bonding is not possible, the Receive Elasticity
Buffers are bypassed, and RXCKSEL must be MID. This clock
mode generates separate RXCLKx± outputs for each receive
channel.
When DECMODE = MID (or open), the 10-bit transmission
characters are decoded using Table 28 and Table 29.
Received Special Code characters are decoded using the
Cypress column of Table 29.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using Table 28 and Table 29. Received Special
Code characters are decoded using the Alternate column of
Table 29.
In all settings where the Decoder is enabled, the receive paths
may be operated as separate channels or bonded to form
various multi-channel buses.
Receive BIST Operation
The Receiver interfaces contain internal pattern generators
that can be used to validate both device and link operation.
• decoding the received transmission characters back into
• comparing generated BIST patterns with received
• generation of ODD parity on the decoded characters.
Data and Special Character codes
characters to permit at-speed link and device testing
These generators are enabled by the associated BOE[x]
signals listed in Table 10 (when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated receive
channel becomes a pattern generator and checker by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation symbols. This provides a predictable yet pseudo-
random sequence that can be matched to an identical LFSR
in the attached Transmitter(s). If the receive channels are
configured for common clock operation (RXCKSEL ≠ MID)
each pass is preceded by a 16-character Word Sync
Sequence. When synchronized with the received data stream,
the associated Receiver checks each character in the
Decoder with each character generated by the LFSR and
indicates compare errors and BIST status at the RXSTx[2:0]
bits of the Output Register. See Table 24 for details.
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator/checker in the associated
Receive channel (or the BIST generator in the associated
Transmit channel). When BISTLE returns LOW, the values of
all BOE[x] signals are captured in the BIST Enable Latch.
These values remain in the BIST Enable Latch until BISTLE is
returned HIGH. All captured signals in the BIST Enable Latch
are set HIGH (i.e., BIST is disabled) following a device reset
(TRSTZ is sampled LOW).
When BIST is first recognized as being enabled in the
Receiver, the LFSR is preset to the BIST-loop start-code of
D0.0. This D0.0 character is sent only once per BIST loop. The
status of the BIST progress and any character mismatches is
presented on the RXSTx[2:0] status outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXSTx[2:0] indicates 010b or 100b for one character period
per BIST loop to indicate loop completion. This status can be
used to check test pattern progress. These same status values
are presented when the Decoder is bypassed and BIST is
enabled on a receive channel.
The status reported on RXSTx[2:0] by the BIST state machine
are listed in Table 24. When Receive BIST is enabled, the
same status is reported on the receive status outputs
regardless of the state of DECMODE.
The specific patterns checked by each receiver are described
in detail in the Cypress application note “HOTLink Built-In
Self-Test.”
CYP(V)(W)15G0401DXB when RXCKSEL = MID is identical
to that in the CY7B933 and CY7C924DX, allowing interop-
erable systems to be built when used at compatible serial
signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by sixteen, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
When the receive paths are configured for common clock
operation (RXCKSEL ≠ MID), each pass must be preceded by
a 16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations.
This is automatically generated by the transmitter when its
local RXCKSEL ≠ MID and Encoder is enabled (TXMODE[1]
≠ LOW).
The
sequence
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
compared
Page 24 of 53
by
the
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