MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 21

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

2.5.2.1
There are two restrictions for correct usage of the PLL block:
When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet
these constraints.
2.5.2.2
The value of the PLLDVF field determines the allowable
2.5.2.3
The multiplier block output frequency ranges depend on the input clock frequency as shown in Table 11.
2.5.2.4
The frequency delivered to the core, extended core, and peripheral depends on the value of the CLKCTRL[RNG] bit as shown
in Table 12.
This bit along with the CKSEL determines the frequency range of the core clock.
Freescale Semiconductor
Note:
Note:
Note:
Field Value
PLLDVF
•
•
CLKCTRL[RNG] Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
300 ≤ [Pre-Divided Clock × (PLLMLTF + 1)] ≤ 600 MHz
The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10.5–19.5 MHz.
The output frequency of the PLL multiplier must be in the range 300-600 MHz.
The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–9.
This table results from the allowed range for F
frequency of the Pre-Divided Clock.
This table results from the allowed range for F
Multiplier Block (Loop) Output Range
PLL Multiplier Restrictions
Division Factors and Corresponding CLKIN Frequency Range
Multiplication Factor Range
Allowed Core Clock Frequency Range
1
0
Divide
Factor
1
2
3
4
5
6
7
8
9
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Table 10. CLKIN Frequency Ranges by Divide Factor Value
CLKIN Frequency Range
10.5 to 19.5 MHz
31.5 to 58.5 MHz
52.5 to 97.5 MHz
73.5 to 100 MHz
94.5 to 100 MHz
63 to 100 MHz
84 to 100 MHz
Table 12. F
21 to 39 MHz
42 to 78 MHz
Table 11. PLLMLTF Ranges
Loop
vco
, which is F
. The minimum and maximum multiplication factors are dependent on the
vco
CLKIN
Frequency Ranges
Loop
frequency range, as shown in Table 10.
300/Pre-Divided Clock
Minimum PLLMLTF Value
Pre-Division by 1
Pre-Division by 2
Pre-Division by 3
Pre-Division by 4
Pre-Division by 5
Pre-Division by 6
Pre-Division by 7
Pre-Division by 8
Pre-Division by 9
modified by CLKCTRL[RNG].
Allowed Range of F
300 ≤ F
150 ≤ F
vco
vco
≤ 600 MHz
≤ 300 MHz
vco
Comments
600/Pre-Divided Clock
Maximum PLLMLTF Value
Specifications
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