MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 49

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

3.4.2
Table 31 shows the MSC7115 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET
3.4.3
After a power-on reset, the PLL is bypassed and the device is directly clocked from the
clock, the system initializes using the boot loader program that resides in the internal ROM. After initialization, the
DSP core can enable the PLL and start the device operating at a higher speed. The MSC7115 can boot from an
external host through the HDI16 or download a user program through the I
by configuring the
3.4.3.1
If the MSC7115 device boots from an external host through the HDI16, the port is configured as follows:
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note:
Freescale Semiconductor
BM[1–0]
Signal
SWTE
HDSP
H8BIT
•
•
•
•
•
•
Operate in Non-DMA mode.
Operate in polled mode on the device side.
Operate in polled mode on the external host side.
External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
8- or 16-bit mode as specified by the
Data strobe as specified by the
When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
. For details, refer to the Reset chapter of the MSC711x Reference Manual.
BM1
0
0
1
1
Reset Configuration Pins
Boot
Determines boot mode.
Determines watchdog functionality.
Configures HDI16 strobe polarity.
Configures HDI16 operation mode.
HDI16 Boot
BM[1–0]
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Description
signals sampled at the rising edge of
BM0
0
1
0
1
HDSP
Table 31. Reset Configuration Signals
Table 32. Boot Mode Settings
H8BIT
and
0
01
1x
0
1
0
1
0
1
HDDS
pin.
External host via HDI16 with the PLL disabled.
I
External host via the HDI16 with the PLL enabled.
Reserved.
2
C.
Boot from HDI16 port.
Boot from I2C.
Reserved.
Watchdog timer disabled.
Watchdog timer enabled.
Host Data strobes active low.
Host Data strobes active high.
HDI16 port configured for 16-bit operation.
HDI16 port configured for 8-bit operation.
pins.
PORESET,
2
as shown in Table 32.
C port. The boot operating mode is set
Settings
Boot Source
Hardware Design Considerations
CLKIN
pin. Using this input
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