MB15F02L Fujitsu Media Devices, MB15F02L Datasheet - Page 8

• Manufacturer Part Number: MB15F02L
• Description: Dual Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu Media Devices

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8
MB15F02L
(2) Data Setting
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Table3. Test Purpose Bit Setting
LSB
Note: Divide ratio less than 5 is prohibited.
C
N
1
1
H
H
T
1
L
L
Programmable Counter
Divide
16383
ratio
(R)
C
N
2
5
6
2
CNT1, 2
N1 to N11
A1 to A7
SW IF/RF
FC IF/RF
LDS
Note: Data input with MSB first.
L
D
S
3
RF
W
IF/
S
4
H
H
T
2
L
L
14
R
0
0
1
RF
IF/
C
5
F
: Control bit
: Divide ratio setting bits for the programmable counter (5 to 2,047)
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
: Phase control bit for the phase detector
: LD/fout signal select bit
(16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL)
A
6
1
13
R
0
0
1
A
7
2
12
R
0
0
1
A
8
3
LD/fout pin state
Outputs fp
Outputs fr
Outputs fp
Outputs fr
11
R
Data Flow
A
0
0
1
9
4
10
A
5
10
R
0
0
1
RF.
IF.
RF.
IF.
11
A
6
R
9
0
0
1
12
A
7
13
N
1
R
8
0
0
1
14
N
2
R
7
0
0
1
15
N
3
16
N
R
4
6
0
0
1
17
N
5
R
5
0
0
1
18
N
6
19
R
4
0
0
1
N
7
20
N
8
R
3
1
1
1
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
21
N
9
R
10
2
0
1
1
22
N
MSB
11
23
N
R
1
1
0
1