RC2324DPL ETC, RC2324DPL Datasheet - Page 21

• Manufacturer Part Number: RC2324DPL
• Description: Single Device Data/fax Modem Data Pump
• Manufacturer: ETC

3.0 Software Interface
3.1 Interface Memory
The DSP communicates with the host by means of a dual-port, interface memory
The interface memory in the DSP contains thirty-two 8-bit registers, labeled
register 00 through 1F. Each register can be read from, or written into, by both the
host and the DSP. The host communicates with the DSP interface memory via the
microprocessor bus.
The host can control modem operation by writing control bits to DSP interface
memory and writing parameter values to DSP RAM through the interface
memory. The host can monitor modem operation by reading status bits from DSP
interface memory and reading parameter values from DSP RAM through
interface memory.
3.2 Interface Memory Map
A memory map of DSP interface memory identifying the contents of the 32
addressable registers is shown in Table 3-1. These 8-bit registers may be read or
written during any host read or write cycle. In order to operate on a single bit or
group of bits in a register, the host must read a register then mask out unwanted
data. When writing a single bit or group of bits in a register, the host must
perform a read-modify-write operation. That is, the host must read the entire
register, set or reset the necessary bits without altering the other register bits, then
write the unaffected and modified bits back into the interface memory register.
3.3 Interface Memory Bit Functions
Table 3-2 summarizes the functions of the individual bits in the interface memory.
Bits in the interface memory are referred to using the format Z:Q. The register
number is denoted by Z (00 through iF) and the bit number is located by Q (0
through 7, where 0 = LSB).
D96V24DSA
3-1