GS1503 Gennum Corporation, GS1503 Datasheet - Page 51

• Manufacturer Part Number: GS1503
• Description: HD Embedded Audio Codec
• Manufacturer: Gennum Corporation

2.6.5 ECC Error Detection & Correction
The GS1503 performs BCH(31,25) forward error detection
and correction as described in SMPTE 299M. The error
correction for audio data packets with audio group DID set
in DATAIDA[1:0] is activated when ECCA_ON bit 0 of Host
Interface register 013h is set HIGH. Similarly, error
correction for audio data packets with audio group DID set
in DATAIDB[1:0] is activated when ECCB_ON bit 1 of Host
Interface register 013h is set HIGH
When a one-bit error is detected in a bit array of the ECC
protected region of the audio data packet with audio group
DID set in DATAIDA[1:0], ECCA_ERR bit 1 in Host Interface
register 015h is set HIGH. When a one-bit error is detected
in the ECC protected region of the audio data packet with
audio group DID set in DATAIDB[1:0], the ECCB_ERR bit 5
in Host Interface register 015h is set HIGH. In both cases,
the ERROR external pin will also be set HIGH.
Register Settings
2.6.6 Audio Data Packet Error Detection
When the 1-255 count sequence in the Data Block Number
(DBN) word of audio data packets with audio group DID set
in DATAIDA[1:0] is discontinuous, the DBNA_ERR bit 3 of
Host Interface register 015h will be set HIGH. When the1-
255 count sequence in the DBN word of audio data packets
with audio group DID set in DATAIDB[1:0] is discontinuous,
the DBNB_ERR bit 7 of Host Interface register 015h will be
set HIGH.
The GS1503 will check the parity (bit 8) for the CLK, CH1-4
and ECC0-5 words in the embedded audio data packets.
When a parity bit error is detected in audio data packets
with
ADPB8A_ERR bit 2 of Host Interface register 015h will be
NO_CORRECTB[11:0]
NO_CORRECTA[11:0]
CORRECTB[11:0]
CORRECTA[11:0]
audio
ECCB_ERR
ECCA_ERR
ECCB_ON
ECCA_ON
NAME
group
DID
Ch5-8 Audio data packet ECC error detection
(1: Detection)
Ch1-4 Audio data packet ECC error detection
(1: Detection)
Ch5-8 correctable packets in one video frame
Ch5-8 un-correctable packets in one video frame
Ch1-4 correctable packets in one video frame
Ch5-8 un-correctable packets in one video frame
Ch5-8 Audio data packet error correction (1: ON)
Ch1-4 Audio data packet error correction (1: ON)
set
in
DATAIDA[1:0],
DESCRIPTION
the
51
A bit array is defined as all 24 bits of bit 0. The next bit
array is all 24 bits of bit 1, and so on through to bit 7. Up to
8 bits in error can be corrected, providing each bit error is
in a different bit array. When there are two bits in error in the
same 24-bit array, the errors will be detected, but not
corrected. When there are more than two bits in error in a
single bit array, the errors will not be detected or corrected.
The number of audio data packets corrected in one video
frame will be reported in the corresponding Host Interface
registers CORRECTA[11:0] and CORRECTB[11:0]. The
GS1503 will also report the number of audio data packets
which could not be corrected in one video frame in the
corresponding Host Interface registers NO_CORRECTA[11:0]
and NO_CORRECTB[11:0].
set HIGH. When a parity bit error is detected in audio data
packets with audio group DID set in DATAIDB[1:0], the
ADPB8B_ERR bit 6 of Host Interface register 015h will be
set HIGH.
The GS1503 will re-calculate the audio data packets
Checksum and compare against the embedded Checksum
word. When a Checksum error is detected in audio data
packets with audio group DID set in DATAIDA[1:0], the
ADPCSA_ERR bit 0 of Host Interface register 015h will be
set HIGH. When a Checksum error is detected in audio
data packets with audio group DID set in DATAIDB[1:0], the
ADPCSB_ERR bit 4 of Host Interface register 015h will be
set HIGH.
When any of the above errors are detected, the ERROR
external pin will also be set HIGH.
ADDRESS
01C
01D
015
016
017
018
019
01A
01B
013
BIT
3-0
7-0
3-0
7-0
3-0
7-0
3-0
7-0
5
1
1
0
SETTING
1
1
-
-
-
-
-
-
DEFAULT
15879 - 1
0
0
0
0
0
0
1
1