GS1522 Gennum Corporation, GS1522 Datasheet - Page 11

• Manufacturer Part Number: GS1522
• Description: Hd-linx (tm) THDTV Serial Digital Serializer
• Manufacturer: Gennum Corporation

The GO1515 is a very clean frequency source and,
because of the internal high Q resonator, is an order of
magnitude more immune to external noise as compared to
on-chip VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V. The control
voltage around the average LFA voltage is 500 x Ι
produces
ƒ = Kƒ x 500 x Ι
5.4. Phase Lock Loop Frequency Synthesis
The GS1522 requires the HDTV parallel clock (74.25 or
74.25/1.001MHz) to synthesize a serial clock which is 20
times the parallel clock frequency (1.485MHz) using a
phase locked loop (PLL). This serial clock is then used to
strobe the output serial data. Figure 16 illustrates this
operation. The VCO is normally free-running at a frequency
close to the serial data rate. A divide-by-20 circuit converts
the free running serial clock frequency to approximately that
of the parallel clock. Within the phase detector, the divided-
by-20 serial clock is then compared to the reference
parallel clock from the PCLK_IN pin (2). Based on the
leading or lagging alignment of the divided clock to the
input reference clock, the serial data output is synchronized
to the incoming parallel clock.
5.5. Lock Logic
Logic is used to produce the PLL_LOCK (15) signal which
is based on the LFS signal and phase lock signal. When
there is no data input, the integrator charges and eventually
saturates at either end. By sensing the saturation of the
integrator, it is determined that no data is present. If there is
no data present or phase lock is low, the lock signal is
made LOW. Logic signals are used to acquire the
frequency by sweeping the integrator. Injecting a current
into the summing node of the integrator achieves the
sweep. The sweep is disabled when phase lock is
asserted. The direction of the sweep is changed when LFS
saturates at either end.
GENNUM CORPORATION
PCLK_IN
Fig. 16 Phase Lock Loop Frequency Synthesis
two frequencies off
GS1522 PLL
P
/2.
PHASE
DETECTOR
DIVIDE-BY-20
from the
GO1515
VCO
centre
P
/2. This
by
11
6. LBCONT
The LBCONT pin (91) is used to adjust the loop bandwidth
by externally changing the internal charge pump current.
For maximum loop bandwidth, connect LBCONT to the
most positive power supply. For medium loop bandwidth,
connect LBCONT through a pull-up resistor (R
low loop bandwidth, leave LBCONT floating. The formula
below shows the change in the loop bandwidth using
R
where LBW
left floating.
7. LOOP BANDWIDTH OPTIMIZATION
Since the feed back loop has only digital circuits, the small
signal analysis does not apply to the system. The effective
loop bandwidth scales with the amount of input jitter
modulation index. The following table summarizes the
relationship between input jitter modulation index and
bandwidth when R
Typical Application Circuit for the location of R
TABLE 1: Relationship Between Input Jitter Modulation Index and
Bandwidth
The product of the input jitter modulation (IJM) and the
bandwidth (BW) is a constant. In this case, it is 282.9kHzUI.
The loop bandwidth automatically reduces with increasing
input jitter, which results in the cleanest signal possible.
Using a series combination of R
an on-chip resistor (see the Typical Application Circuit) can
reduce the loop bandwidth of the GS1522. The parallel
combination of the resistors is directly proportional to the
bandwidth factor. For example, the on-chip 500Ω resistor
yields 282.9kHzUI. If a 50Ω resistor is connected in parallel,
the effective resistance will be (50:500) 45.45Ω. This
resistance yields a bandwidth factor of
[282.9 x (45.45/500)] = 25.72kHzUI
The capacitance C
chosen such that the RC factor is 50µF. For example,
R
PULL-UP.
CP1
INPUT JITTER
MODULATION
=50Ω requires C
INDEX
0.05
0.10
0.20
0.50
LBW
NOMINAL
=
LBW
BANDWIDTH
is the loop bandwidth when LBCONT is
CP1
CP3
5.657MHz
2.828MHz
1.414MHz
NOMINAL
565.7kHz
CP3
=1µF.
in series with the R
and C
×
CP3
(
----------------------------------------------------- -
(
25kΩ
CP1
5kΩ
are not used. See the
(jitter modulation x BW)
and C
BW JITTER FACTOR
+
+
R
R
282.9kHzUI
282.9kHzUI
282.9kHzUI
282.9kHzUI
PULL UP
PULL UP
CP3
CP1
CP1
–
in parallel to
–
PULL-UP
and C
should be
522 - 26 - 02
)
)
). For
CP3
.