GS1522 Gennum Corporation, GS1522 Datasheet - Page 9

• Manufacturer Part Number: GS1522
• Description: Hd-linx (tm) THDTV Serial Digital Serializer
• Manufacturer: Gennum Corporation

DETAILED DESCRIPTION
DETAILED DESCRIPTION
DETAILED DESCRIPTION
DETAILED DESCRIPTION
The GS1522 HDTV Serializer is a bipolar integrated circuit
used to convert parallel data into serial format according to
the SMPTE 292M standard. The device encodes both 8-bit
and 10-bit TTL compatible parallel signals producing a
serial data rate of 1.485Gb/s. The device operates from a
single 5V supply and is available in a 128 pin MQFP
package.
The functional blocks within the device include the input
latches, interleaver, sync detector, parallel to serial
converter, SMPTE scrambler, NRZ to NRZ(I) converter, two
internal
multiplication and lock detect circuitry.
1. INPUT LATCHES
The 20-bit input latch accepts either 3.3V or 5V CMOS/TTL
inputs. The input data is buffered and then latched on the
rising edge of the PCLK_IN pin (2). The output of the latch
is a differential signal for increased noise immunity. Further
noise isolation is provided by the use of separate power
supplies.
2. INTERLEAVER
The interleaver takes the 20-bit wide parallel data (Y and C)
and reduces it internally to a 10-bit wide word by alternating
the Y and C data words according to SMPTE 292M, section
6.1.
3. SYNC DETECTOR
The sync detector looks for the reserved words 000-003
and 3FC-3FF in 10-bit hexadecimal, or 00-03 and FC-FF in
8-bit hexadecimal used in the TRS-ID sync word. When
there is an occurrence of all zeros or all ones in the eight
higher order bits, the lower two bits are forced to zeros or
GENNUM CORPORATION
BYPASS
cable
drivers,
10k
Fig. 13 BYPASS Circuit
5k
PLL
for
V
EE
20x
5k
V
parallel
CC
BIAS
clock
9
ones respectively. This allows the system to be compatible
with 8-bit and 10-bit data. For non-SMPTE standard parallel
data, a logic input Sync Detect Disable pin (96) is available
to disable this feature.
4. SCRAMBLER
The scrambler is a linear feedback shift register used to
pseudo-randomize the incoming data according to the fixed
polynomial (X
the output serial stream. The NRZ to NRZ(I) converter uses
another polynomial (X+1) to convert a long sequence of
ones to a series of transitions, minimizing polarity effects. To
disable these features, set the BYPASS pin (16) HIGH.
5. SLEW PHASE LOCK LOOP (S-PLL)
An innovative feature of the GS1522 is the slew phase lock
loop (S-PLL). When a step phase change is applied to the
PLL, the output phase gains constant rate of change with
respect to time. This behavior is termed slew. Figure 14
shows an example of input and output phase variation over
time for slew and linear (conventional) PLLs. Since the
slewing is a non-linear behavior, the small signal analysis
cannot be done in the same way as it is for the standard
PLL. However, it is still possible to plot input jitter transfer
characteristics at a constant input jitter modulation.
Slew PLLs offer several advantages such as excellent noise
immunity. The loop corrects small input jitter modulation
immediately because of the infinite bandwidth. Therefore,
the small signal noise of the VCO is cancelled immediately.
The GS1522 uses a very clean, external VCO called the
GO1515 (refer to the GO1515 Data Sheet for details).
Another advantage is the bi-level digital phase detector
which
predominantly independent of the data transition density.
The loop bandwidth of a conventional tri-stable charge
provides
9
+X
4
+1). This minimizes the DC component in
constant
loop
bandwidth
522 - 26 - 02
that
is