IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 39

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST AC-
CESS PORT
as described in the IEEE 1149.1 standards.
isters plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the Test
Data Input (TDI) pin, and shifted out of the registers via the Test Data
Output (TDO) pin. Both TDI and TDO are clocked at a rate determined
by TCK.
The IDT82V2048 supports the digital Boundary Scan Specification
The boundary scan architecture consists of data and instruction reg-
TRST
TDI
TCK
TMS
parallel latched output
Digital output pins
(Test Access Port)
Controller
IDR (Device Identification Register)
TAP
BSR (Boundary Scan Register)
IR (Instruction Register)
BR (Bypass Register)
Figure - 21. JTAG Architecture
Control<6:0>
Digital input pins
39
Register), IDR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure-21 for architecture.
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR)
select the test to be executed or the data register to be accessed or
both.
Table-17 for details of the codes and the instructions related.
The JTAG boundary scan registers includes BSR (Boundary Scan
The IR (Instruction Register) with instruction decode block is used to
The instructions are shifted in LSB first to this 3-bit register. See
Select
Tristate Enable
MUX
INDUSTRIAL TEMPERATURE RANGES
TDO