GS1503-CFZ Gennum Corp., GS1503-CFZ Datasheet - Page 32

• Manufacturer Part Number: GS1503-CFZ
• Description: HD EMBEDDED AUDIO CODEC
• Manufacturer: Gennum Corp.

1.11 ARBITRARY DATA PACKETS
The GS1503 can multiplex arbitrary data packets according
to SMPTE 291M. Typically, this consists of linear time code
(LTC), vertical interval time code (VITC) or other user data,
which is multiplexed once per video field. The GS1503 has
1.11.1 Arbitrary Data Multiplexing In External Pin Mode
This is the default mode for multiplexing arbitrary data
packets. The GS1503 will set the PKTENO external pin
HIGH when arbitrary data can be input to the device. Two
VCLK cycles after PKTENO goes HIGH, the user should set
the PKTEN arbitrary packet enable pin HIGH. Two VCLK
cycles after PKTEN is set HIGH, arbitrary data can be input
at the PKT[7:0] bus. See Figure 30 for timing.
PKTENO
PKT[7:0]
Arbitrary
PKTEN
Packet
MSB
VCLK
LSB
2 CLKs
Contents set in Host Interface registers
Y/C
Arbitrary Data Packet Timing
Arbitrary Data Input Enable
Arbitrary Data
2 CLKs
b
/ C
r
[19:0]
Fig. 30 Arbitrary Data Packet Input Timing Diagram
Fig. 29 Arbitrary Data Packet Structure
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Automatically generated by the GS1503
VIN[19:0]
PKTENO
PKTEN
PKT[7:0]
Parity bit
two modes in which arbitrary data can be multiplexed into
the Luma channel of the video data stream. A maximum of
255 user data words can be multiplexed in one packet.
Figure 29 shows the structure of the arbitrary data packet.
NOTE: Arbitrary data packets will not be multiplexed in the
two lines following the video switching point (see Section
1.8).
The user is required to enter the following arbitrary data:
Data ID (DID), Secondary Data ID (SDID), Data Count (DC)
and User Data Words (UDW: maximum of 255), via the
PKT[7-0] pins. This GS1503 automatically generates the
Ancillary Data Flag (ADF), Checksum (CS) and bit 8 (Parity
Bit) and bit 9 (Not bit 8).
The PKTENO pin will be set HIGH on all video lines except
the two lines following the video switching point. For
example, with the default setting of line 7 field 1, PKTENO
will not be set HIGH on lines 8 and 9. The switching point is
set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface
registers for field 1 and field 2 respectively. See Section 1-8.
User Data Words
Not b8
GS1503
Arbitrary Data
2 CLKs
2 CLKs
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