GS1559-CBE2 Gennum Corp., GS1559-CBE2 Datasheet - Page 39

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GS1559-CBE2

Manufacturer Part Number
GS1559-CBE2
Description
HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver
Manufacturer
Gennum Corp.
Datasheet

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GS1559 Preliminary Data Sheet
4.7.4 HVF Timing Signal Generation
The GS1559 extracts critical timing parameters from either the received TRS
signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator
(FW_EN/DIS = HIGH).
Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F)
timing are all extracted and presented to the application layer via the H:V:F status
output pins.
The H signal timing is configurable via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking, or TRS based
blanking, (see
Section
4.10.6).
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H output is HIGH for the entire horizontal blanking period, including the
EAV and SAV TRS words. This is the default H timing used by the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
output will be HIGH for the entire horizontal blanking period as indicated by the H
bit in the received TRS ID words.
The timing of these signals is shown in
Figure
4-3.
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November 2004
Proprietary and Confidential
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