HV9906 Supertex Inc, HV9906 Datasheet - Page 6

• Manufacturer Part Number: HV9906
• Description: Simple Off-Line/PFC & >9V DC/DC Switcher
• Manufacturer: Supertex Inc

Design Information
Programming On Time
The instantaneous voltage applied to the V
gate drive output on time for the VCO cycle. The on time is
inversely proportional to the voltage applied to the V
be calculated using the following equation:
Where the effective control range of V
and 6V. For V
17.8 S.
Depending on the converter topology and worst case operating
conditions the minimum on time and thus the duty cycle may be
programmed.
Programming the Sense Inputs
The PS and NS sense pins are regulated at +1V and each needs
to be programmed to source the same current at the converter
output regulation set point.
In order to calculate the values of R
sense current, which will avoid integrator saturation, must be
determined. Since by design the circuit will inherently soft start
from its lowest frequency, the designer only needs to establish the
lowest operating frequency (f
to minimum converter output power under closed loop control.
Once this frequency is established the maximum PS pin sense
current I
V
Where C
is the minimum saturation level of the integrators and f
minimum operating frequency of the converter. Inserting these
values the above equation can be simplified.
For the general case, where at regulation neither sensed node
might be at ground potential, the following equation may be used
to calculate the required R
most negative value that the node will see during starting or normal
operation.
Once the value of R
currents at the regulation point can be calculated and the value of
R
P
NSENSE
NS
V
ON
can be determined as follows.
, can be calculated using the following equation.
PS(MAX)
MIN
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] FAX: [phone] www.supertex.com




. 0
I
I
I
R
I
R
PS
PS
PS
PS
is the minimum value of the integrator capacitors, V
085
PS
NS
(
(
(
MAX
MAX
MAX
, which occurs during start up when V
ON
I
NS
)
)
)
1
1
= 0V P(V
V
V
. 0
V
. 1
C
(
PS
65
ON
. 0
1
MIN
14
I
V
V
V
I
PS
95
has been determined the I
NS
PSENSE




NSENSE
(
MAX
)
R
10
V
10
ON
V
PS
PS
PSENSE
(
)
SAT
) defaults to a nominal maximum of
20
resistor value where V
MIN
(
10
MIN
6
) for the design, which corresponds
)
10
f
f
MIN
MIN
NS
12
ON
and R
)
is limited between 0.2V
6
ON
f
PS,
MIN
pin determines the
the maximum
PS
PSENSE(MIN)
and I
PSENSE
ON
MIN
pin and may
NS
is the
=
sense
is the
SAT
6
Where I
output regulation, V
voltage with respect to +1V and V
sensed node voltage with respect +1V. V
be less than +1V and V
V
Example 1.
For a converter operating at a minimum frequency of 50KHz and
sensing a –1V feedback node voltage with respect to ground, the
resistors connected in series with the PS and NS pins will be
determined as follows.
To provide a margin of safety let I
configuration the resistor in series with the PS pin is connected to
ground, the sense node voltage V
Example 2.
For a converter operating at a minimum frequency of 100KHz and
sensing a +0.5V feedback node voltage with respect to ground, the
resistors connected in series with the PS and NS pins will be
determined as follows.
To provide a margin of safety let I
configuration the most negative value of V
startup at which time it is 0V.
Protection
The HV9906 used as a current source is inherently protected in the
case of an output short. Over voltage protection is easily
accomplished, in the flyback-buck application for example, with no
more than two diodes. Simple protection for voltage mode
applications, and other topologies is easy to accomplish. Call for
more information.
PSENSE
.
NS
= I
I
I
I
I
R
R
R
R
PS
PS
PS
PS
PS
NS
PS
NS
PS
(
(
MAX
MAX
= average current in the NS and PS pins at stable
I
I
NS
NS
)
)
1
1
1
1
V
V
V
V
NSENSE
. 1
. 1
1
1
I
14
14
I
V
V
V
I
V
V
V
I
PS
PS
NS
NS
PSENSE
PSENSE
NSENSE
NSENSE
NSENSE
(
(
MAX
MAX
R
R
10
V
10
V
is the most negative sensed node
PS
PS
PSENSE
PSENSE
)
)
(
(
10
10
MIN
MIN
is always more negative than
)
)
5
5
1
5
1
PS(MAX)
PS(MAX)
PSENSE
PSENSE(MIN)
1
10
10
10
5
(
10
1
10
200
1
0
1
100
) 1
1
5
4
10
6
6
(
(
is the least negative
= 5 A. Since in this
k
= 10 A. In this
10
) 0
0
k
0
. 0
NSENSE
11
PSENSE(MIN)
5
6
400
200
) 5
7 .
= 0V.
6
4 .
5
200
k
k
A
100
A
5
and V
A
k
A
k
occurs during
PSENSE
HV9906
07/23/02
must